Interrupt Set-Pending Register (Ispr); Interrupt Clear-Pending Register (Icpr) - ST STM32F0 Series Programming Manual

Core peripherals
4.2.4

Interrupt set-pending register (ISPR)

Address offset: 0x0100
Reset value: 0x0000 0000
This register forces interrupts into pending state, and shows which interrupts are pending.
31 30 29 28
rs rs rs rs
15 14 13 12
rs rs rs rs
Bits 31:0 SETPEND: Interrupt set-pending bits
Write:
Read:
Writing 1 to the ISPR bit corresponding to an interrupt that is pending:
Writing 1 to the ISPR bit corresponding to a disabled interrupt:
4.2.5

Interrupt clear-pending register (ICPR)

Address offset: 0x0180
Reset value: 0x0000 0000
Removes pending state from interrupts and shows which interrupts are pending.
31 30 29 28
rc_w1 rc_w1 rc_w1 rc_w1
15 14 13 12
rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:0 CLRPEND: Interrupt clear-pending bits
Write:
0: No effect
1: Removes the pending state of an interrupt
Read:
0: Interrupt is not pending
1: Interrupt is pending
Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
72/91
27 26 25
rs rs rs
11 10 9
rs rs rs
0: No effect
1: Changes interrupt state to pending
0: Interrupt is not pending
1: Interrupt is pending
– has no effect.
– sets the state of that interrupt to pending.
27 26 25
rc_w1 rc_w1 rc_w1
11 10 9
rc_w1 rc_w1 rc_w1
Doc ID 022979 Rev 1
24 23 22 21
SETPEND[31:16]
rs rs rs
8 7 6
SETPEND[15:0]
rs rs rs
24 23 22 21
CLRPEND[31:16]
rc_w1 rc_w1 rc_w1 rc_w1
8 7 6
CLRPEND[15:0]
rc_w1 rc_w1 rc_w1 rc_w1
20 19 18
rs rs rs rs
5 4 3 2
rs rs rs rs
20 19 18
rc_w1 rc_w1 rc_w1
5 4 3 2
rc_w1 rc_w1 rc_w1
PM0215
17 16
rs rs
1 0
rs rs
17 16
rc_w1 rc_w1
1 0
rc_w1 rc_w1