The Stm32 Cortex-M0 Instruction Set; Instruction Set Summary; Table 14. Cortex-M0 Instructions - ST STM32F0 Series Programming Manual

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The STM32 Cortex-M0 instruction set

This chapter is the reference material for the Cortex-M0 instruction set description in a User
Guide. The following sections give general information:
Section 3.1: Instruction set summary on page 31
Section 3.2: CMSIS intrinsic functions on page 35
Section 3.3: About the instruction descriptions on page 36
Each of the following sections describes a functional group of Cortex-M0 instructions.
Together they describe all the instructions supported by the Cortex-M0 processor:
Section 3.4: Memory access instructions on page 41
Section 3.5: General data processing instructions on page 48
Section 3.6: Branch and control instructions on page 59
Section 3.7: Miscellaneous instructions on page 61
3.1

Instruction set summary

The processor implements a version of the thumb instruction set.
supported instructions.
In Table 14:
● Angle brackets, <>, enclose alternative forms of the operand
●
Braces, {}, enclose optional operands
● The operands column is not exhaustive
●
Op2 is a flexible second operand that can be either a register or a constant
● Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions.
Table 14.
Mnemonic
ADCS
ADD{S}
ADR
ANDS
ASRS
B{cc}
Cortex-M0 instructions
Operands
{Rd,} Rn, Rm Add with carry
{Rd,} Rn, <Rm|#imm> Add
Rd, label PC-relative address to register
{Rd,} Rn, Rm Bitwise AND
{Rd,} Rm, <Rs|#imm> Arithmetic shift right
label Branch {conditionally}
Doc ID 022979 Rev 1
The STM32 Cortex-M0 instruction set
Brief description
Table 14 lists the
Flags Page
3.5.1 on
N,Z,C,V
page 49
3.5.1 on
N,Z,C,V
page 49
3.4.1 on
-
page 42
3.5.2 on
N,Z
page 51
3.5.3 on
N,Z,C
page 52
3.6.1 on
-
page 59
31/91