Ands, Orrs, Eors And Bics - ST STM32F0 Series Programming Manual

PM0215
3.5.2

ANDS, ORRS, EORS and BICS

Logical AND, OR, exclusive OR and bit clear.
Syntax
ANDS {Rd,} Rn, Rm
ORRS {Rd,} Rn, Rm
EORS {Rd,} Rn, Rm
BICS {Rd,} Rn, Rm
where:
●
'Rd' is the destination register
● 'Rn' is the register holding the first operand and is the same as the destination register.
●
'Rm' is the second register.
Operation
The AND, EOR, and ORR instructions perform bitwise AND, exclusive OR, and inclusive OR
operations on the values in Rn and Rm.
The BIC instruction performs an AND operation on the bits in Rn with the logical negation of
the corresponding bits in the value of Rm.
The condition code flags are updated on the result of the operation,
on page
Restrictions
In these instructions, Rd, Rn, and Rm must only specify R0-R7.
Condition flags
These instructions:
●
update the N and Z flags according to the result
●
do not affect the C or V flag.
Examples
ANDS
ORRS
ANDS
EORS
BICS
39.
R2, R2, R1
R2, R2, R5
R5, R5, R8
R7, R7, R6
R0, R0, R1
Doc ID 022979 Rev 1
The STM32 Cortex-M0 instruction set
seeThe condition flags
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