Max Ii Cpld Epm2210 System Controller - Altera Cyclone III LS Reference Manual

2–6
Table 2–4. Cyclone III LS Device Pin Count and Usage (Part 2 of 2)
Function
LEDs
Clocks or Oscillators
EEPROM
Device I/O Total:
Note to Table 2–4:
(1) The LCD signals are multiplexed with HSMB_D[65:75] and therefore not included in the total pin count.

MAX II CPLD EPM2210 System Controller

The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the
following purposes:
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1
The development kit includes the anti-tamper example design in the
<install_dir>\kits\cycloneIIILS_3cls200_fpga\examples\max2\at_example\
readme_at_example.txt directory.
Figure 2–3
and external circuit connections as a block diagram.
Figure 2–3. MAX II CPLD EPM2210 System Controller Block Diagram
PC
Embedded
Blaster
Encoder
Power
Measurement
Results
Cyclone III LS FPGA Development Board Reference Manual
I/O Standard
1.8-V CMOS
1.8-V / 2.5-V CMOS + LVDS
2.5-V CMOS
FPGA configuration from flash memory
Power consumption monitoring
Virtual JTAG interface for PC-based GUI
Control registers for clocks
Control registers for remote system update
Anti-Tamper example design
illustrates the MAX II CPLD EPM2210 System Controller's functionality
JTAG Control
SLD-HUB
Virtual-JTAG
LTC2418
Controller
Power
Calculations
I/O Count
5 1 INIT_DONE
5 2 differential clock input, 1 clock input
2 —
390
Anti-Tamper
Example Design
Information
Register
Decoder
Control
Register
PFL
Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Special Pins
3CLS
FLASH
SSRAM
GPIO
MAX-II
© October 2009 Altera Corporation