Max V Cpld 5M2210 System Controller - Altera Cyclone V GT FPGA Reference Manual

2–6
Table 2–3. Cyclone V GT Device I/O Pin Count
Function
SDI video port
Push buttons
DIP switches
Character LCD
LEDs
SMA
Clock or Oscillators
ASSP
Configuration
Total I/O Used:
Table 2–4
the board.
Table 2–4. Cyclone V GT Transceivers
HSMA port
HSMA port or SDI (supports HSMA by default)
HSMB port
PCI Express x4 port
Total Transceivers

MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the
following purposes:
■ FPGA configuration from flash
■ Power measurement
■ Control and status registers (CSRs) for remote system update
Cyclone V GT FPGA Development Board
Reference Manual
I/O Standard
2.5-V CMOS + XCVR
1.5-V CMOS
1.5-V CMOS
1.5-V CMOS
1.5-V CMOS
CMOS
1.8-V CMOS + LVDS
1.5-V CMOS
—
lists the Cyclone V GT device transceiver count and usage by function on
Function
Chapter 2: Board Components
MAX V CPLD 5M2210 System Controller
I/O Count Special Clock Pins
6 —
4 —
8 —
2 —
8 —
1 —
Four differential clocks, 1
9
1 single-ended
8 —
30 —
540
Count
3
1
4
4
12
August 2017 Altera Corporation