ST STM32G4 Series Reference Manual page 1851

RM0440
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 CLFSDET: Clear late frame synchronization detection flag.
This bit is write only.
Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register.
This bit is not used in AC'97or SPDIF mode
Reading this bit always returns the value 0.
Bit 5 CAFSDET: Clear anticipated frame synchronization detection flag.
This bit is write only.
Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register.
It is not used in AC'97or SPDIF mode.
Reading this bit always returns the value 0.
Bit 4 CCNRDY: Clear Codec not ready flag.
This bit is write only.
Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register.
This bit is used only when the AC'97 audio protocol is selected in the SAI_xCR1 register.
Reading this bit always returns the value 0.
Bit 3 Reserved, must be kept at reset value.
Bit 2 CWCKCFG: Clear wrong clock configuration flag.
This bit is write only.
Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register.
This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the
SAI_xCR1 register.
Reading this bit always returns the value 0.
Bit 1 CMUTEDET: Mute detection flag.
This bit is write only.
Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register.
Reading this bit always returns the value 0.
Bit 0 COVRUDR: Clear overrun / underrun.
This bit is write only.
Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register.
Reading this bit always returns the value 0.
40.5.14 SAI clear flag register (SAI_BCLRFR)
Address offset: 0x03C
Reset value: 0x0000 0000
31 30 29 28 27
Res. Res. Res. Res. Res. Res.
15 14 13 12 11
Res. Res. Res. Res. Res. Res.
26 25 24 23
Res. Res. Res.
10 9 8 7
Res. Res. Res. CLFSDET CAFSDET CCNRDY
RM0440 Rev 4
22 21 20
Res. Res. Res.
6 5 4
w w w
Serial audio interface (SAI)
19 18 17
Res. Res. Res.
3 2 1
CWCKCF CMUTE
Res.
G DET
w w
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16
Res.
0
COVRUD
R
w
1858