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9 ClOCK TiMeR
9.4
interrupt Function
The clock timer can generate an interrupt at the falling edge of 128 Hz*, 64 Hz*, 32 Hz, 16 Hz*, 8 Hz, 4 Hz*, 2 Hz
and 1 Hz signals. Software can enable or mask any of these frequencies to generate interrupts.
Figure 9.4.1 is the timing chart of the clock timer.
Address
Bit
Frequency
D0
128 Hz
D1
64 Hz
FF41H
D2
32 Hz
D3
16 Hz
D0
8 Hz
D1
4 Hz
FF42H
D2
2 Hz
D3
1 Hz
128 Hz interrupt request *
64 Hz interrupt request *
32 Hz interrupt request
16 Hz interrupt request *
8 Hz interrupt request
4 Hz interrupt request *
2 Hz interrupt request
1 Hz interrupt request
As shown in Figure 9.4.1, an interrupt is generated at the falling edge of each frequency signal (128 Hz*, 64 Hz*, 32
Hz, 16 Hz*, 8 Hz, 4 Hz*, 2 Hz, 1 Hz). At this time, the corresponding interrupt factor flag (IT0*, IT1*, IT2, IT3*,
IT4, IT5*, IT6, IT7) is set to "1." The interrupt mask registers (EIT0*, EIT1*, EIT2, EIT3*, EIT4, EIT5*, EIT6,
EIT7) are used to enable or mask each interrupt factor. However, regardless of the interrupt mask register setting, the
interrupt factor flag is set to "1" at the falling edge of the corresponding signal.
* Not supported in the S1C63003
9.5
i/O Memory of Clock Timer
Table 9.5.1 shows the I/O addresses and the control bits for the clock timer.
Address
Register name R/W Default
FF16H D3 MDCKE (*5)
R/W
D2 SGCKE
R/W
D1 SWCKE
R/W
D0 RTCKe
R/W
FF40H D3 0 (*3)
D2 0 (*3)
D1 TMRST (*3)
D0 TMRun
R/W
9-2
Figure 9.
4.1 Timing chart of clock timer
Table 9.
5.1 Control bits of clock timer
Setting/data
0
1 Enable
0
1 Enable
0
1 Enable
0
1 Enable
R
– (*2)
R
– (*2)
W
(Reset) 1 Reset
0
1 Run
Seiko epson Corporation
Clock timer timing chart
0 Disable
Integer multiplier clock enable
0 Disable
Sound generator clock enable
0 Disable
Stopwatch timer clock enable
0 Disable
Clock timer clock enable
–
Unused
–
Unused
0 Invalid
Clock timer reset (writing)
0 Stop
Clock timer Run/Stop
S1C63003/004/008/016 TeChniCal Manual
Function
(Rev. 1.1)
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