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aPPenDiX e SuMMaRY OF nOTeS
Oscillation circuit
• When high speed CPU operations are not necessary, you should operate the peripheral circuits with the setting
shown below.
- CPU operating clock:
- OSC3 oscillation circuit: Off (When the OSC3 clock is not necessary for peripheral circuits.)
- Clock manager:
• Since several tens of µsec to several tens of msec are necessary for the oscillation to stabilize after turning the
OSC3 oscillation circuit on. Consequently, you should switch the CPU operating clock (OSC1 → OSC3) after
allowing for a sufficient waiting time once the OSC3 oscillation goes on. The oscillation start time will vary
somewhat depending on the resonator and externally attached parts. Refer to the oscillation start time example
indicated in the "Electrical Characteristics" chapter.
• When switching the clock from OSC3 to OSC1, be sure to switch OSC3 oscillation off with separate instruc-
tions. Using a single instruction to process simultaneously can cause a malfunction of the CPU.
• Both the OSC1 and OSC3 oscillation circuits stop oscillating when the CPU enters SLEEP mode. To prevent
the CPU from a malfunction when it resumes operating from SLEEP mode, switch the CPU clock to OSC1
before placing the CPU into SLEEP mode.
Watchdog timer
• When the watchdog timer is being used, the software must reset it within 3-second cycles.
• Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled state
(not used) before generating an interrupt (NMI) if it is not used.
Clock timer
• Be sure to read timer data in the order of low-order data (TM[3:0]) then high-order data (TM[7:4]).
• The clock timer count clock does not synch with the CPU clock. Therefore, the correct value may not be ob-
tained depending on the count data read and count-up timings. To avoid this problem, the clock timer count
data should be read by one of the procedures shown below.
- Read the count data twice and verify if there is any difference between them.
- Temporarily stop the clock timer when the counter data is read to obtain proper data.
• When resetting the clock timer (TMRST = "1"), do not start the clock timer (TMRUN = "1") simultaneously.
If both control bits are set to "1," the clock timer may not reset properly.
Stopwatch timer
• The interrupt factor flag should be reset after resetting the stopwatch timer.
• Be sure to data reading in the order of SWD[3:0] → SWD[7:4] → SWD[11:8].
• When data that is held by a LAP input is read, read the capture buffer renewal flag CRNWF after reading the
SWD[11:8] and check whether the data has been renewed or not. (S1C63004/008/016)
• When performing a processing such as a LAP input preceding with 1 Hz interrupt processing, read the
LAP data carry-up request flag LCURF before processing and check whether carry-up is needed or not.
(S1C63004/008/016)
Programmable timer
• When reading counter data, be sure to read the low-order 4 bits (PTDx[3:0]) first. The high-order 4 bits
(PTDx[7:4]) are latched when the low-order 4 bits are read and they are held until the next reading of the low-
order 4 bits. In 16-bit timer mode, the high-order 12 bits are held by reading the low-order 4 bits, be sure to
read the low-order 4 bits first. When the CPU is running with the OSC1 clock and the programmable timer is
running with the OSC3 clock, stop the timer before reading the counter data to read the proper data.
• The programmable timer actually enters RUN/STOP status in synchronization with the falling edge of the input
clock after writing to the PTRUNx register. Consequently, when "0" is written to the PTRUNx register, the
timer enters STOP status at the point where the counter is decremented (-1). The PTRUNx register maintains
"1" for reading until the timer actually stops.
aP-e-2
OSC1
Disable the clock supply to unnecessary peripheral circuits.
Seiko epson Corporation
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
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