Epson S1C63003 Technical Manual page 123

SDP: Data input/output permutation select register (FF59h•D1)
Selects the serial data input/output permutation.
When "1" is written: MSB first
When "0" is written: LSB first
Reading: Valid
Select whether the data input/output permutation will be MSB first or LSB first. At initial reset, this register is set
to "0."
SCPS[1:0]: Clock format select register (FF59h•D[3:2])
Selects the timing for reading in the serial data input from the SIN (P32) terminal.
• When positive polarity (SCPS1 = "0") is selected for the synchronous clock:
During receiving, the serial data is read into the built-in shift register at the rising edge of the SCLK signal when
the SCPS0 register is "0" or at the falling edge of the SCLK signal when the SCPS0 register is "1." The shift
register is sequentially shifted as the data is fetched.
During transmitting, the serial data output to the SOUT (P31) terminal changes at the rising edge of the clock
input or output from/to the SCLK (P30) terminal. The data in the shift register is shifted at the rising edge of the
SCLK signal when the SCPS0 register is "0" or at the falling edge of the SCLK signal when the SCPS0 register
is "1."
• When negative polarity (SCPS1 = "1") is selected for the synchronous clock:
During receiving, the serial data is read into the built-in shift register at the falling edge of the SCLK signal when
the SCPS0 register is "0" or at the rising edge of the SCLK signal when the SCPS0 register is "1." The shift reg-
ister is sequentially shifted as the data is fetched.
During transmitting, the serial data output to the SOUT (P31) terminal changes at the falling edge of the clock
input or output from/to the SCLK (P30) terminal. The data in the shift register is shifted at the falling edge of the
SCLK signal when the SCPS0 register is "0" or at the rising edge of the SCLK signal when the SCPS0 register
is "1."
At initial reset, this register is set to "0."
enCS: SRDY_SS enable register (P33 port function selection) (FF5ah•D0)
Enables the serial interface function of P33. Use this register with ESREADY.
When "1" is written: Enabled (Serial interface)
When "0" is written: Disabled (I/O port)
Reading: Valid
When ENCS is enabled, the P33 terminal can be used as SRDY output or SS input terminal in slave mode (SMOD
= "0"). At initial reset, this register is set to "0."
eSReaDY: SRDY_SS function select register (FF5ah•D1)
Selects the P33 port function when ENCS = "1."
When "1" is written: SRDY output
When "0" is written: SS input
Reading: Valid
The P33 port function can be selected from SRDY output and SS input in slave mode (SMOD = "0"). At initial
reset, this register is set to "0."
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
Table 13. 8.3 Configuration of synchronous clock format
SCPS[1:0] Polarity
3 Negative (SCLK)
2 Negative (SCLK)
1 Positive (SCLK)
0 Positive (SCLK)
Seiko epson Corporation
13 SeRial inTeRFaCe
Phase
Rising edge (↑)
Falling edge (↓)
Falling edge (↓)
Rising edge (↑)
13-11