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14 lCD DRiVeR
14.2.2
Power Source for lCD Driving
The power source for driving LCD can be selected from the internal power supply and an external power supply.
When the internal power supply is selected, the internal LCD system voltage regulator is enabled to generate the
LCD drive voltages V
–V
C1
V
–V
to the LCD driver when the LPWR register is set to "1."
C1
C3
The LCD system voltage regulator generates the reference voltage V
× 2, V
× 3, or V
= V
= V
C1
C3
C1
When the internal power supply is used in the S1C63003, the reference voltage (V
cording to the supply voltage V
1. Internal power supply (V
2. Internal power supply (V
In the S1C63004/008/016, the reference voltage can be selected using use the VCREF register.
For more information on the LCD system voltage regulator, refer to the "Power Supply" chapter.
When using an external power supply, select a drive voltage configuration from the following 3 types and supply the
LCD drive voltage to the V
1. External power supply 1/3 bias (for 4.5 V panel) V
2. External power supply 1/3 bias (for 3.0 V panel) V
3. External power supply 1/2 bias (for 3.0 V panel) V
For the external connection diagram when an external supply is used, refer to the "Power Supply" chapter.
Note that the power control using the LPWR register is necessary even if an external power supply is used.
14.2.3
Segment Option
Segment allocation
Note: Refer to Appendix D, "Mask Data Creation Procedure," for mask data creation including segment
allocation and precautions.
The display memory addresses and data bits can be allocated to a segment terminal individually. This makes
design easy by increasing the degree of freedom with which the LCD panel can be designed.
Figure 14.2.3.1 shows an example of the relationship between the LCD segments (on the panel) and the display
memory for the case of 1/4 duty.
Display memory allocation
Address
D3
F010H
d
F011H
p
Pin address allocation
COM0
SEG10
1 1 , D 1
( f )
SEG11
1 0 , D 0
( a )
Output specification
Each of the SEG0 to SEG35 terminals of the S1C63016, the SEG0 to SEG29 terminals of the S1C63008, the
SEG0 to SEG19 terminals of the S1C63004, or the SEG0 to SEG9 terminals of the S1C63003 can be configured
for either segment signal output or DC output (V
When DC output is selected, either complementary output or N-channel open drain output can be selected as the
output specification for each terminal pair. When DC output is selected, the data corresponding to COM0 of each
segment terminal is output. DC output can be performed even if the LCD system voltage regulator is off (LPWR
= "0").
Other SEG terminals can be used only for segment signal output. DC output cannot be selected.
14-2
. The LCD system voltage regulator starts operating and outputs the LCD drive voltages
C3
× 1/2, V
= V
= V
C1
C2
C3
by mask option.
DD
reference) 1/3 bias (for 3.0 V panel)
C2
reference) 1/3 bias (for 3.0 V panel)
C1
–V
terminals.
C1
C3
DD
DD
DD
Data bit
D2
D1
D0
c
b
g
f
COM1
COM2
COM3
1 1 , D 0
1 0 , D 2
1 0 , D 3
( e )
( c )
( d )
1 1 , D 2
1 0 , D 1
1 1 , D 3
( g )
( b )
( p )
Figure 14.
2.3.1 Segment allocation
DD
Seiko epson Corporation
or V
and generates two other voltages (V
C1
C2
× 3/2) by boosting or reducing V
C2
= V
C2
= V
C3
= V
, V
= V
C3
C1
C2
a
f
a
c
g
e
d
SEG10 SEG11
and V
binary output) by mask option.
SS
S1C63003/004/008/016 TeChniCal Manual
/V
.
C1
C2
or V
) should be selected ac-
C1
C2
b
COM0
COM1
COM2
c
COM3
p
(Rev. 1.1)
C2
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