Programmable Timer; Configuration Of Programmable Timer - Epson S1C63003 Technical Manual

11

Programmable Timer

11.1

Configuration of Programmable Timer

The S1C63004/008/016 has built-in two (Ch.A and Ch.B) units of programmable timers. The S1C63003 has a built-in
single unit of programmable timer (Ch.A). The timer configurations of Ch.A and Ch.B are shown below. This module
allows the software to configure timer channels.
Model
8-bit mode
S1C63016
Timer 0 and Timer 1
S1C63008
(8 bits × 2 channels)
S1C63004
Timer 0
S1C63003
(8 bits × 1 channel)
Figure 11.1.1 shows the configuration of the programmable timer.
Each timer has an 8-bit down counter and an 8-bit reload data register. The down counter counts the internal clock of
which the frequency can be selected with software. Furthermore, Timers 0 and 2 also have an event counter function
to count the clock input from the EVIN_A (P10) and EVIN_B (P22) terminals. When the down counter underflows
during counting with the specified clock, the timer outputs the underflow and interrupt signals and resets the counter
to its initial value. The reload data register is used to set the initial value.
The underflow signal of Timer 1 (S1C63004/008/016) is used as the source clock of the R/F converter and serial
interface, this makes it possible to program a flexible R/F converter count clock and the transfer rate of the serial
interface.
Each timer of the S1C63004/008/016 has an 8-bit compare data register in addition to the above registers. This regis-
ter is used to store data to be compared with the contents of the down counter. When the timer is set to PWM mode,
the timer outputs the compare match signal if the contents between the down counter and the compare data register
are matched, and an interrupt occurs at the same time. Also the compare match signal is used with the underflow
signal to generate a PWM waveform.
The signal generated by the programmable timer can be output from the TOUT_A (P11) or TOUT_B (P23) port
terminal.
P10 port
EVIN_A
(P10)
Timer 0
PTRUN0
Run/Stop
Timer 0
clock
f
OSC1
Clock
PTPS0[3:0]
manager
Timer 0 clock selection
f
OSC3
f /16 (2,048Hz)
OSC1
Interrupt Interrupt
request
control circuit
TOUT_A P11 port
Output
(P11)
control
PTOUT_A
Output control
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
Table 11. 1.1 Configuration of programmable timer
Ch.A
16-bit mode
Timer 0 + Timer 1
(16 bits × 1 channel)
Timer 0
Timer function setting FCSEL_A
PLPUL_A
Pulse polarity setting
EVCNT_A
Event counter
mode setting
1/2
(a) S1C63003 timer Ch.A (Timer 0)
Seiko epson Corporation
11 PROGRaMMaBle TiMeR
8-bit mode
Timer 2 and Timer 3
(8 bits × 2 channels)
Timer 2
(8 bits × 1 channel)
Not available
PTRST0
Timer 0 reset
Timer
control
circuit
Ch.B
16-bit mode
Timer 2 + Timer 3
(16 bits × 1 channel)
Not available
Reload data register
RLD0[7:0]
8-bit down counter
Data buffer
PTD0[7:0]
Underflow signal
11-1