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11 PROGRaMMaBle TiMeR
11.3
Basic Counter Operation
This section explains the basic count operation when each timer is used as an individual 8-bit timer.
Each timer has an 8-bit down counter and an 8-bit reload data register.
The reload data register RLDx[7:0] is used to set the initial value to the down counter.
By writing "1" to the timer reset bit PTRSTx, the down counter loads the initial value set in the reload register. There-
fore, down-counting is executed from the stored initial value by the count clock.
The PTRUNx register is provided to control the RUN/STOP for each timer. By writing "1" to this register after pre-
setting the reload data to the down counter, the down counter starts counting down. Writing "0" stops the input count
clock and the down counter stops counting. This control (RUN/STOP) does not affect the counter data. The counter
maintains its data while stopped, and can restart counting continuing from that data.
The counter data can be read via the data buffer PTDx[7:0] in optional timing. However, the counter has the data hold
function the same as the clock timer, that holds the high-order data (PTDx[7:4]) when the low-order data (PTDx[3:0])
is read in order to prevent the borrowing operation between low- and high-order reading, therefore be sure to read
the low-order data first.
The counter reloads the initial value set in the reload data register when an underflow occurs through the count down.
It continues counting down from the initial value after reloading.
In addition to reloading the counter, this underflow signal controls the interrupt generation and pulse (TOUT_A/
TOUT_B signal) output. The underflow signal of Timer 1 (S1C63004/008/016) is also used to generate the clock to
be supplied to the serial interface and R/F converter.
PTRUNx
PTRSTx
RLDx[7:0]
Count clock
PTDx7
PTDx6
PTDx5
PTDx4
PTDx3
PTDx2
PTDx1
PTDx0
11.4
event Counter Mode (Timers 0 and 2)
Timer 0/Timer 2 has an event counter function that counts an external clock input to an I/O port. Table 11.4.1 lists
the timers and their clock input ports.
Timer 0 (Ch.A)
Timer 2 (Ch.B) *
This function is selected by writing "1" to the counter mode select register EVCNT_A/EVCNT_B. This sets the
corresponding I/O port to input mode and enables the port to send the input signal to Timer 0/Timer 2 as the count
clock. At initial reset, EVCNT_A/EVCNT_B is set to "0" and Timer 0/Timer 2 is configured as a normal timer that
counts the internal clock.
11-4
A6H
Preset
Figure 11.
3.1 Basic operation timing of down counter
Table 11.
4.1 Event counter clock input port
Timer
External clock input terminal
EVIN_A (P10)
EVIN_B (P22) *
Seiko epson Corporation
F3H
Reload &
underflow interrupt
Control register
EVCNT_A
EVCNT_B *
* S1C63004/008/016
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
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