Epson S1C63003 Technical Manual page 218

In event counter mode, the timer starts counting at the first event clock.
Figure E.
• Since the TOUT_A/TOUT_B signal is generated asynchronously from the PTOUT_A/PTOUT_B register, a
hazard within 1/2 cycle is generated when the signal is turned on and off by setting the register.
• When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3 oscillation
on, prior to using the programmable timer. However the OSC3 oscillation circuit requires several tens of µsec
to several tens of msec after turning the circuit on until the oscillation stabilizes. Therefore, allow an adequate
interval from turning the OSC3 oscillation circuit on to starting the programmable timer. Refer to the "Oscil-
lation Circuit and Clock Control" chapter, for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in off state.
• For the reason below, pay attention to the reload data write timing when changing the interval of the program-
mable timer interrupts while the programmable timer is running.
The programmable timer counts down at the falling edge of the input clock and at the same time it generates
an interrupt if the counter underflows. Then it starts loading the reload data to the counter and the counter data
is determined at the next rising edge of the input clock (period shown in as ➀ in the figure).
Count clock
Counter data
(continuous mode)
Underflow (interrupt is generated)
To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter data is
determined including the reloading period ➀. Be especially careful when using the OSC1 (low-speed clock) as
the clock source of the programmable timer and the CPU is operating with the OSC3 (high-speed clock).
• The programmable timer count clock does not synch with the CPU clock. Therefore, the correct value may not
be obtained depending on the count data read and count-up timings. To avoid this problem, the programmable
timer count data should be read by one of the procedures shown below.
- Read the count data twice and verify if there is any difference between them.
- Temporarily stop the programmable timer when the counter data is read to obtain proper data.
i/O port
• When an I/O ports in input mode is changed from high to low by the pull-down resistor, the fall of the waveform
is delayed on account of the time constant of the pull-down resistor and input gate capacitance. Hence, when
fetching input data, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
Count clock
PTRUNx (RD)
"1" (RUN)
writing
PTRUNx (WR)
PTDx[7:0] 42H
Figure E. 1.1 Timing chart for RUN/STOP control (timer mode)
Count clock
PTRUNx (RD)
"1" (RUN)
writing
PTRUNx (WR)
PTDx[7:0] 42H 41H 40H 3FH 3EH
1.2 Timing chart for RUN/STOP control (event counter mode)
03H 02H 01H
Figure E. 1.3 Reload timing for programmable timer
Seiko epson Corporation
aPPenDiX e SuMMaRY OF nOTeS
"0" (STOP)
writing
41H 40H 3FH 3EH 3DH
"0" (STOP)
writing
3DH
➀
00H 25H 24H
Counter data is determined by reloading.
(Reload data = 25H)
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