Sound Generator; Configuration Of Sound Generator; Controlling Operating Clock; Buzzer Output Control - Epson S1C63003 Technical Manual

Cmos 4-bit single chip microcontroller
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15

Sound Generator

15.1

Configuration of Sound Generator

The S1C63003/004/008/016 has a built-in sound generator for generating a buzzer signal. Hence, the generated
buzzer signal can be output from the BZ terminal. Aside permitting the respective setting of the buzzer signal fre-
quency and sound level to 8 stages, it permits the adding of a digital envelope by means of duty ratio control. It also
has a one-shot output function for outputting key operated sounds. Figure 15.1.1 shows the configuration of the sound
generator.
SGCKE
f
OSC1
Clock
manager
f
/128
OSC1
BZSHT
BZSTP
SHTPW
Note: If the BZ terminal is used to drive an external component that consumes a large amount of current
such as a bipolar transistor, design the pattern of traces on the printed circuit board so that the
operation of the external component does not affect the IC power supply. Refer to "Precautions on
Mounting" in the Appendix for more information.
15.2

Controlling Operating Clock

To generate the buzzer signal, the clock for the sound generator must be supplied from the clock manager by writing
"1" to the SGCKE register in advance.
SGCKE
1
0
If it is not necessary to run the sound generator, stop the clock supply by setting SGCKE to "0" to reduce current
consumption.
15.3

Buzzer Output Control

The BZ signal generated by the sound generator is output from the BZ (P12) terminal by setting "1" for the buzzer output
enable register BZE. The I/O control register IOC12 and data register P12 settings are ineffective while the BZ signal is
being output. When BZE is set to "0," the P12 port is configured as a general-purpose DC input/output port.
BZ output (P12 terminal)
Note: Since it generates the buzzer signal that is out of synchronization with the BZE register, hazards
may at times be produced when the signal goes on/off due to the setting of the BZE register.
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
BZFQ[2:0]
BDTY[2:0]
Programmable
Duty ratio
dividing circuit
control circuit
One-shot buzzer
control circuit
Figure 15.
1.1 Configuration of sound generator
Table 15.
2.1 Controlling sound generator clock
Sound generator clock
Programmable dividing circuit input clock: f
One-shot buzzer control circuit input clock: f
BZE register
"0"
Figure 15.
3.1 Buzzer signal output timing chart
Seiko epson Corporation
15 SOunD GeneRaTOR
ENON
Envelope
addition circuit
Buzzer output
control circuit
BZE
(32 kHz)
OSC1
/ 128 (256 Hz)
OSC1
Off
"1"
"0"
ENRST
ENRTM
BZ (P12) terminal
15-1

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