Halt And Sleep - Epson S1C63003 Technical Manual

In this case, since several tens of µsec to several tens of msec are necessary for the oscillation to stabilize after turning
the OSC3 oscillation circuit on, you should switch over the clock after the stabilization time has elapsed.
The oscillation start time will vary somewhat depending on the resonator and on the externally attached parts. Refer
to the oscillation start time example indicated in the "Electrical Characteristics" chapter.
When switching the clock from OSC3 to OSC1 (CLKCHG = "1" → "0"), be sure to switch OSC3 oscillation off with
separate instructions. Using a single instruction to process simultaneously may cause a malfunction of the CPU.
Figure 7.2.1 indicates the status transition diagram for the clock switch over.
High speed operation
OSC1
OSC3
CPU clock
Interrupt
OSC1
OSC3
CPU clock
* The return destination from the standby status becomes the program execution status prior to
shifting to the standby status.
7.3

halT and SleeP

The S1C63003/004/008/016 supports both HALT and SLEEP modes for power saving during standby.
halT mode
The CPU enters HALT mode and stops operating when it executes the HALT instruction. However, timer coun-
ters and peripheral circuits continue operating since the oscillation circuit operates in HALT mode. Reactivating
the CPU from HALT status is done by generating a hardware interrupt request including NMI.
SleeP mode
The CPU enters SLEEP mode when it executes the SLP instruction. In this mode, the CPU and oscillation circuits
(both OSC1 and OSC3) stop operating. Current consumption can considerably be reduced, as SLEEP mode stop
all the peripheral circuits that operate with the internal clocks. To prevent improper operation after the CPU wakes
up, be sure to run the CPU with the OSC1 clock before setting the CPU into SLEEP mode.
The system can only be reactivated from SLEEP mode by a key input interrupt request from a P0x or P1x port. To
ensure that the system enters and cancels SLEEP mode properly, follow the procedure shown below to configure/
confirm the CPU clock, interrupt flag, the P0x (P1x) I/O port used to cancel SLEEP mode, and the port input
level.
1. Set the CPU system clock switching register CLKCHG to "0." (The OSC1 clock is selected.)
2. Set the interrupt select register SIPxx to "1." (The P0x (P1x) I/O port interrupt is selected.)
3. Set the interrupt mask register EIKxx to "1." (The P0x (P1x) I/O port interrupt is enabled.)
4. Set the key input interrupt noise reject frequency select register NRSPxx to "0H." (The noise rejector is by-
passed.)
5. Write "1" to the interrupt factor flag IKxx. (the P0x (P1x) interrupt factor flag is reset.)
6. Set the interrupt flag (I flag) to "1." (Interrupts are enabled.)
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
Program Execution Status
RESET
Low speed operation
CLKCHG=0
ON OSC1
ON OSC3
OSC3 CPU clock
CLKCHG=1
*
HALT instruction
HALT status
ON
ON or OFF
STOP
Standby Status
Figure 7. 2.1 Status transition diagram for clock switch over
Seiko epson Corporation
7 OSCillaTiOn CiRCuiT anD ClOCK COnTROl
OSCC=0
ON
ON
OSC1
OSCC=1
*
Interrupt
(Key input interrupt)
SLEEP status
OSC1
OSC3
CPU clock
Low speed and
low power operation
OSC1 ON
OSC3 OFF
CPU clock OSC1
SLP instruction
OFF
OFF
STOP
7-3