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11 PROGRaMMaBle TiMeR
When "0" is written to these registers, the noise rejector is not used and the counting is done directly by an ex-
ternal clock input to the EVIN_A (P10) or EVIN_B (P22) terminal. These registers are effective only when the
timer is used in the event counter mode. At initial reset, these registers are set to "0."
The S1C63003 does not include a register at FF90H.
eVCnT_a: Timer 0 counter mode select register (FF80h•D2)
eVCnT_B: Timer 2 counter mode select register (FF90h•D2) – S1C63004/008/016
Selects the counter mode for each timer.
When "1" is written: Event counter mode
When "0" is written: Timer mode
Reading: Valid
The counter modes for Timers 0 and 2 are selected from either the event counter mode or timer mode.
When "1" is written to these registers, event counter mode is selected. In this mode, Timers 0 and 2 count the
external clock input from the EVIN_A (P10) and EVIN_B (P22) terminals, respectively. When "0" is written,
timer mode is selected. In this mode, the timer counts the internal clock selected by the PTPSx[3:0] register. This
selection is effective even when Ch.A/Ch.B is used in 16-bit timer mode. At initial reset, these registers are set to
"0."
The S1C63003 does not include a register at FF90H.
MOD16_a: Timer 0–1 16-bit timer mode select register (FF80h•D3) – S1C63004/008/016
MOD16_B: Timer 2–3 16-bit timer mode select register (FF90h•D3) – S1C63016
Selects 8-bit or 16-bit timer mode.
When "1" is written: 16-bit timer mode
When "0" is written: 8-bit timer mode
Reading: Valid
These registers are used to select whether Timers 0 and 1 in Ch.A or Timers 2 and 3 in Ch.B are used as two chan-
nels of independent 8-bit timers or one channel of combined 16-bit timer. When "0" is written to the register, the
timers are set to 8-bit timer mode. When "1" is written, the timers are set to 16-bit timer mode. When Ch.A/Ch.B
is used in 16-bit timer mode, Timer 1/Timer 3 operates with the Timer 0/Timer 2 underflow signal as the count
clock (both timer mode and event counter mode). In 16-bit timer mode, the Timer 0/Timer 2 register settings are
effective for timer RUN/STOP control and count clock frequency selection (Timer 1/Timer 3 registers are inef-
fective). However, the PWM output function must be controlled using the Timer 1/Timer 3 control register. The
reload data must be preset to Timer 0/Timer 2 and Timer 1/Timer 3 separately using each PTRSTx register. At
initial reset, these registers are set to "0."
FF90H•D3 in the S1C63004/008 and FF80H•D3 in the S1C63003 are read only bits and always "0" will be read.
The S1C63003 does not include a register at FF90H.
PTOuT_a: TOuT_a output control register (FF81h•D0)
PTOuT_B: TOuT_B output control register (FF91h•D0) – S1C63004/008/016
Controls TOUT signal outputs.
When "1" is written: TOUT output On
When "0" is written: TOUT output Off
Reading: Valid
When "1" is written to the register, the corresponding TOUT_A/TOUT_B signal is output from the P11/P23 ter-
minal. When TOUT output is enabled, the I/O port is automatically set to output mode and it outputs the TOUT
signal sent from the timer. The I/O control register (IOC11/IOC23) and the data register (P11/P23) are ineffective.
When this register is set to "0," the I/O port control registers become effective. At initial reset, these registers are
set to "0."
The S1C63003 does not include a register at FF91H.
11-12
Seiko epson Corporation
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
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