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18 inTeGeR MulTiPlieR
MDCKe: integer multiplier clock enable register (FF16h•D3)
Controls the operating clock supply to the integer multiplier.
When "1" is written: On
When "0" is written: Off
Reading: Valid
When "1" is written to MDCKE, the integer multiplier operating clock (CPU operating clock selected by OSCC
and CLKCHG) is supplied from the clock manager. If it is not necessary to run the integer multiplier, stop the
clock supply by setting MDCKE to "0" to reduce current consumption. At initial reset, this register is set to "0."
SR[7:0]: Source register (FF71h, FF70h)
Used to set multipliers and divisors.
Set the low-order 4 bits of data to SR[3:0] and the high-order 4 bits to SR[7:4]. This register maintains the latest
set value until the next writing, so it is not necessary to set data for each operation if the same multiplier and
divisor is used in a series of operations. At initial reset, this register is undefined.
DRl[7:0]: Destination register low-order 8 bits (FF73h, FF72h)
Used to set multiplicands and low-order 8 bits of dividends.
Set the low-order 4 bits of data to DRL[3:0] and the high-order 4 bits to DRL[7:4]. Data written to this register
is loaded to the arithmetic circuit when an operation starts (by writing to FF76H•D0), and then a multiplication
or a division is performed in 10 CPU clock cycles (5 bus cycles). After the operation has finished, the low-order
8 bits of the product or the quotient are loaded to this register. However, if an overflow occurs in a division pro-
cess, the quotient is not loaded and the low-order 8 bits of the dividend remains. At initial reset, this register is
undefined.
DRh[7:0]: Destination register high-order 8 bits (FF75h, FF74h)
Used to set high-order 8 bits of dividends.
Set the low-order 4 bits of data to DRH[3:0] and the high-order 4 bits to DRH[7:4].
At the start of a multiplication (by writing "0" to FF76H•D0), the contents in this register are ignored. After 10
CPU clock cycles (5 bus cycles) of multiplication process has finished, the high-order 8 bits of the product are
loaded in this register. In a division process, data written to this register is loaded to the arithmetic circuit when
an operation starts (by writing "1" to FF76H•D0), and then a division is performed in 10 CPU clock cycles (5 bus
cycles). After the operation has finished, the remainder is loaded to this register. However, if an overflow occurs
in a division process, the remainder is not loaded and the high-order 8 bits of the dividend remains. At initial reset,
this register is undefined.
CalMD: Calculation mode select register/operation status (FF76h•D0)
Selects multiplication or division mode and starts operation.
When "1" is written: Selects/starts division
When "0" is written: Selects/starts multiplication
When "1" is read: Under operating
When "0" is read: Operation has finished
Writing to this register starts the specified operation. After that, this register is set to "1" and returns to "0" when
the multiplication or division process has finished.
At initial reset, this register is reset to "0."
ZF: Zero flag (FF76h•D1)
Indicates whether the operation result is zero or not.
When "1" is read: Zero
When "0" is read: Not zero
Writing: Invalid
ZF is a read-only bit, so writing operation is invalid. At initial reset, this flag is set to "0."
18-4
Seiko epson Corporation
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
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