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3 CPu anD MeMORY
3.3.4
i/O Memory
The peripheral circuits of S1C63003/004/008/016 (timer, I/O, etc.) are interfaced with the CPU in the memory
mapped I/O method. Thus, all the peripheral circuits can be controlled by accessing the I/O memory on the memory
map using the memory operation instructions.
The control registers for the peripheral circuits are located in the I/O memory area as shown in the figure below. Refer
to the Appendix for the register list and descriptions of each peripheral circuit for details of the registers.
Address
FF00H
FF01H
FF03H
FF04H–FF05H SVD circuit
FF10H–FF1BH Clock manager
FF20H–FF3FH I/O ports and input interrupt control
FF40H–FF42H Clock timer
FF44H–FF47H Sound generator
FF48H–FF4DH Stopwatch timer
FF50H–FF52H LCD driver
FF58H–FF5CH Serial interface
FF60H–FF6BH R/F converter
FF70H–FF76H Integer multiplier
FF80H–FF9FH Programmable timer
FFE1H–FFFFH Interrupt controller
3-4
Peripheral circuit
Oscillation circuit
Watchdog timer
Power supply circuit
Figure 3.
3.4.1 I/O memory map
Seiko epson Corporation
S1C63xxx
016
008
004
003
–
–
–
–
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
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