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11 PROGRaMMaBle TiMeR
By writing "1" to PTRSTx, the reload data in the reload register RLDx[7:0] is preset to the counter in Timer x.
When the counter is preset in the RUN status, the counter restarts immediately after presetting. In the case of
STOP status, the reload data is preset to the counter and is maintained. No operation results when "0" is writ-
ten.
The PTRSTx registers are all effective even in 16-bit timer mode, and reload data must be preset to all Timers
separately. Since these bits are exclusively for writing, always set to "0" during reading.
FF92H•D3 in the S1C63004/008 and FF82H•D3 in the S1C63003 are read only bits and always "0" will be read.
The S1C63003 does not include a register at FF92H.
RlD0[7:0]: Timer 0 reload data register (FF85h, FF84h)
RlD1[7:0]: Timer 1 reload data register (FF87h, FF86h) – S1C63004/008/016
RlD2[7:0]: Timer 2 reload data register (FF95h, FF94h) – S1C63004/008/016
RlD3[7:0]: Timer 3 reload data register (FF97h, FF96h) – S1C63016
Sets the initial value for the counter. The reload data written in these registers are loaded to the respective coun-
ters. The counter counts down using the data as the initial value for counting. Reload data is loaded to the counter
when the counter is reset by writing "1" to the PTRSTx register, or when counter underflow occurs. At initial
reset, these registers are set to "00H."
The S1C63004/008 does not include registers at FF96H–FF97H. The S1C63003 does not include registers at
FF86H–FF87H and FF94H–FF97H.
PTD0[7:0]: Timer 0 counter data (FF89h, FF88h)
PTD1[7:0]: Timer 1 counter data (FF8Bh, FF8ah) – S1C63004/008/016
PTD2[7:0]: Timer 2 counter data (FF99h, FF98h) – S1C63004/008/016
PTD3[7:0]: Timer 3 counter data (FF9Bh, FF9ah) – S1C63016
Count data in the programmable timer can be read from these latches. The low-order 4 bits of the count data in
Timer x can be read from PTDx[3:0], and the high-order data can be read from PTDx[7:4]. Since the high-order
4 bits are held by reading the low-order 4 bits, be sure to read the low-order 4 bits first. In 16-bit timer mode, the
high-order 12 bits are held by reading the low-order 4 bits, be sure to read the low-order 4 bits first. Since these
latches are exclusively for reading, the writing operation is invalid. At initial reset, these counter data are set to
"00H."
The S1C63004/008 does not include registers at FF9AH–FF9BH. The S1C63003 does not include registers at
FF8AH–FF8BH and FF98H–FF9BH.
CD0[7:0]: Timer 0 compare data register (FF8Dh, FF8Ch) – S1C63004/008/016
CD1[7:0]: Timer 1 compare data register (FF8Fh, FF8eh) – S1C63004/008/016
CD2[7:0]: Timer 2 compare data register (FF9Dh, FF9Ch) – S1C63004/008/016
CD3[7:0]: Timer 3 compare data register (FF9Fh, FF9eh) – S1C63016
Sets the compare data for PWM output. When the timer is set to PWM mode, the compare data set in this register
is compared with the counter data and outputs the compare match signal if they are matched. The compare match
signal is used for generating an interrupt and controlling the duty ratio of the PWM waveform.
At initial reset, these registers are set to "00H."
The S1C63004/008 does not include registers at FF9EH–FF9FH. The S1C63003 does not include registers at
FF8CH–FF8FH and FF9CH–FF9FH.
11.11
Precautions
• When reading counter data, be sure to read the low-order 4 bits (PTDx[3:0]) first. The high-order 4 bits (PTDx[7:4])
are latched when the low-order 4 bits are read and they are held until the next reading of the low-order 4 bits. In
16-bit timer mode, the high-order 12 bits are held by reading the low-order 4 bits, be sure to read the low-order 4
bits first. When the CPU is running with the OSC1 clock and the programmable timer is running with the OSC3
clock, stop the timer before reading the counter data to read the proper data.
• The programmable timer actually enters RUN/STOP status in synchronization with the falling edge of the input
clock after writing to the PTRUNx register. Consequently, when "0" is written to the PTRUNx register, the timer
enters STOP status at the point where the counter is decremented (-1). The PTRUNx register maintains "1" for
reading until the timer actually stops.
11-14
Seiko epson Corporation
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
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