Appendix C Power Saving; Power Saving By Clock Control - Epson S1C63003 Technical Manual

Appendix C Power Saving

Current consumption will vary dramatically, depending on CPU operating mode, operation clock frequency, and the
peripheral circuits being operated. Listed below are the control methods for saving power.
C.1

Power Saving by Clock Control

Figure C.1.1 illustrates the S1C63003/004/008/016 clock system.
OSC1
oscillation circuit
(32.768 kHz)
OSC3
oscillation circuit
SLEEP On/Off
f
OSC1
divider
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
f
OSC1
System clock
f
OSC3
f
OSC3
divider
f
OSC1
f •1/16–1/256
OSC1
f •1/16–1/256
OSC1
f •1/1–1/256
OSC1
f •1/1–1/256
OSC3
f •1/1–1/256
OSC1
f •1/1–1/256
OSC3
f •1/1–1/256
OSC1
f •1/1–1/256
OSC3
f •1/1–1/256
OSC1
f •1/1–1/256
OSC3
f •1/1–1/256
OSC1
f •1/1–1/256
OSC3
f
OSC1
f
OSC3
f
OSC1
f
OSC3
*1 S1C63016 only *2 S1C63008/016 only *3 S1C63004/008/016 only
Figure C. 1.1 Clock system
Seiko epson Corporation
aPPenDiX C POWeR SaVinG
Oscillation circuit
Gate
HALT
Clock manager
f •1/128
OSC1
Gate
f or f
OSC1 OSC3
Gate
f •1/128
OSC1
Gate
f •1/128
OSC1
Gate
, f •1/128
OSC1
Gate
f •1/16
OSC1
Gate
Gate
Gate
Gate
Gate
Gate
Gate
•1/1–1/4
Gate
•1/1–1/4
•1/1–1/4
Gate
•1/1–1/4
S1C63000 CPU
Internal logic
Watchdog timer
*2
Integer multiplier
Clock timer
Stopwatch timer
Sound generator
LCD system voltage
regulator (booster)
P0 key input interrupt
noise rejector
P1 key input interrupt
*3
noise rejector
FOUT
Programmable
timer 0
Programmable
*3
timer 1
Programmable
*3
timer 2
Programmable
*1
timer 3
*3
Serial interface
R/F converter
aP-C-1