Xilinx Zynq UltraScale+ ZCU208 User Manual page 33

I2C bus I2C1 connects RFSoC U1 PS Bank 500, PL bank 89, and system controller U38 to two
I2C switches (TCA9548A U20 and U22). These I2C1 connections enable I2C communications
with various I2C capable target devices. TCA9548A U20 is pin-strapped to respond to I2C
address 0x74. TCA9548A U22 is pin-strapped to respond to I2C address 0x75.
The following figure shows a high-level view of the I2C1 bus connectivity.
U1
BANK 500
PS I2C1
MIO17/
MIO16
U1
BANK 89
PL I2C1
D9/C9
U38
MPS430
28 P4_1
29 P4_2
The addresses of each target device on the I2C1 U20 and U22 PCA9548A switches are
identified in the following tables.
Table 11: I2C1 TCA9548A U20 Target Device Addresses
TCA9548A U20 (Addr 0x74) Port
0
1
2
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Figure 8: I2C1 Bus Topology
U18
I2C1_SDA/SCL
L/S
U19
L/S
I2C1 Bus Device
EEPROM U16
Si5341 Clock U43
USER Si570 C0 Clock U47
Chapter 3: Board Component Descriptions
U20
TCA9548A
IIC_EEPROM_SDA/SCL
SD0/SC0
S15341_SDA/SCL
SD1/SC1
USER_S1570__C0_SDA/SCL
SD2/SC2
SDA/SCL
USER_MGT_S1570_SDA/SCL
SD3/SC3
8A34001_SDA/SCL
SD4/SC5
CLK104_SDA/SCL
SD5/SC5
RFMC_I2C_SDA/SCL
SD6/SC6
Not Connected
SD7/SC7
0x74
U22
TCA9548A
FMCP_HSPC_II_SDA/SCL
SD0/SC0
USER_SI570_C1_SDA/SCL
SD1/SC1
SYSMON_SDA/SCL
SD2/SC2
PS_DDR4_SODIMM_SDA/SCL
SDA/SCL
SD3/SC3
SFP3_IIC_SDA/SCL
SD4/SC5
SFP2_IIC_SDA/SCL
SD5/SC5
SFP1_IIC_SDA/SCL
SD6/SC6
SFP0_IIC_SDA/SCL
SD7/SC7
0x75
Target Device Address
0X54
0x76
0X5D
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