Xilinx Zynq UltraScale+ ZCU208 User Manual page 25

Table 6: I/O Voltage Rails (cont'd)
ZU48DR
PS Bank 503
PS Bank 504
Notes:
1. The ZCU208 board is shipped with VADJ_FMC set to 1.8V by the MSP430 system controller.
PS DDR4 SODIMM Socket
[Figure 2, callout 2]
The PS-side memory is wired to the Zynq UltraScale+ RFSoC DDRC Bank 504 hard memory
controller. A 64-bit single rank DDR4 SODIMM is inserted into socket J48. The ZCU208 is
shipped with a DDR4 SODIMM installed:
• Manufacturer: Micron
• Part Number: MTA4ATF51264HZ-2G6E1
• Description:
4 GByte DDR4 260-Pin SODIMM
○
Single Rank (x 16-bit components)
○
512 Mb x 64-bit
○
2666 MT/s
○
The ZCU208 ZU48DR RFSoC (ZU48DR supports 2400MT/s) PS DDR interface performance is
documented in the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics
(DS926).
The ZCU208 DDR4 SODIMM interface adheres to the constraints guidelines documented in the
PCB guidelines for DDR4 section of the UltraScale Architecture PCB Design User Guide (UG583).
The DDR4 SODIMM interface is a 40Ω impedance implementation. Other memory interface
details are also available in the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP
Product Guide (PG150).
For additional details, see the Micron MTA4ATF51264HZ-2G6E1 data sheet on the
Technology website.
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU208 board XDC file, referenced in
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Power Net Name Voltage
VCC1V8 1.8V
VCC1V2 1.2V
Appendix B: Xilinx Design
Chapter 3: Board Component Descriptions
Connected To
PS CONFIG I/F
PS_DDR4_SODIMM (64-BIT) I/F
Constraints.
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