Corehc2 Connector Pin Out (Xm655 Only) - Xilinx Zynq UltraScale+ ZCU208 User Manual

CoreHC2 Connector Pin Out (XM655 Only)

Tile
ADC
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Appendix C: HW-XM650/655 Balun Daughter Cards for Gen 3 RFSoC EVM
Figure 27: ADC 16 Lanes
Channel
0 1
2 3
0 1
2 3
0 1
2 3
0 1
2 3
JHC6
ADC224_T0_CH1
ADC224_T0_CH3
ADC225_T1_CH1
ADC225_T1_CH3
ADC226_T2_CH1
ADC226_T2_CH3
ADC227_T3_CH1
ADC227_T3_CH3
JHC8
Send Feedback
JHC5
ADC224_T0_CH0
ADC224_T0_CH2
ADC225_T1_CH0
ADC225_T1_CH2
ADC226_T2_CH0
ADC226_T2_CH2
ADC227_T3_CH0
ADC227_T3_CH2
JHC7
X24154-062520
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