Xilinx Zynq UltraScale+ ZCU208 User Manual page 9

PS MIO[64:77]: Ethernet RGMII
○
• PL I/O connections
PL user DIP switch (8-position)
○
PL user pushbuttons (5, geographic N, S, E, W, C)
○
PL CPU reset pushbutton
○
PL user green LEDs (24)
○
• Security—PSBATT button battery backup
• SYSMON header
• Operational switches (power on/off, PS_PROG_B, boot mode DIP switch)
• Operational status LEDs (INIT, DONE, PS STATUS, PGOOD)
• Power management
• System controller (MSP430)
The ZCU208 provides a rapid prototyping platform that uses the XCZU48DR-2FSVG1517
device. The ZU48DR contains many useful processor system (PS) hard block peripherals exposed
through the multi-use I/O (MIO) interface and a variety of FPGA programmable logic. The
following table lists a brief summary of the resources available within the ZU48DR. Feature set
overview, description, and ordering information is provided in the Zynq UltraScale+ RFSoC Data
Sheet: Overview (DS889).
Table 1: Zynq UltraScale+ RFSoC ZU48DR Features and Resources
SD-FEC
14-bit 5.0 GSPS ADC RF-DAC with DDC
14-bit 10 GSPS RF-DAC with DUC
APU: Quad-core Arm
RTPU: Dual-core Arm
HD I/O
HP I/O
MIO banks
PS GTR 6 Gb/s transceivers
PL GTY 28 Gb/s transceivers
System logic cells
CLB flip-flops
CLB LUTs
Maximum distributed RAM (Mb)
Block RAM blocks
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Feature
Cortex™-A53 MPCore with CoreSight™
®
® Cortex™-R5F MPCore with CoreSight
Chapter 1: Introduction
Resource Count
8
8
8
1
1
96
312
3 banks, total of 78 pins
4 PS-GTRs
16 GTYs
930, 300
850, 560
425, 280
13.0
1080 (38 Mb)
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