Xilinx Zynq UltraScale+ ZCU208 User Manual page 45

IN1: Unused
○
IN2: Unused
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FB_IN: Unused
○
• Outputs:
OUT0: 27 MHz
○
Enabled, LVDS 3.3 V
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OUT1: Unused
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OUT2: 26 MHz
○
Enabled, LVDS 3.3 V
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OUT3: 125 MHz
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Enabled, LVDS 3.3 V
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OUT4: 100 MHz
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Enabled, HCSL 3.3 V
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OUT5: 100 MHz
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Enabled, LVDS 3.3 V
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OUT6: 125 MHz
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Enabled, LVDS 3.3 V
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OUT7: 74.25 MHz [ 74 + 1/4 MHz ]
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Enabled, LVDS 3.3 V
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OUT8: Unused
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OUT9: 33.3333333333333333... MHz [ 33 + 1/3 MHz ]
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Enabled, LVCMOS In-phase 1.8V
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Programmable User SI570 Clocks
[Figure 2, callouts 11 and 12]
The ZCU208 board has three I2C programmable SI570 low-jitter 3.3V LVDS differential
oscillators, two assigned to the DDR4 component memory interface banks (Bank 65 I/F C0: U47
and Bank 69 I/F C1: U130) and one assigned to GTY131 (U48).
On power-up the user clocks default to a pre-programmed output frequency: DDR4 I/F U47 and
U130 to 300.000 MHz and GTY I/F U48 to 156.250 MHz.
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Chapter 3: Board Component Descriptions
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