Xilinx Zynq UltraScale+ ZCU208 User Manual page 34

Table 11: I2C1 TCA9548A U20 Target Device Addresses (cont'd)
TCA9548A U20 (Addr 0x74) Port
3
4
5
6
7
Table 12: I2C1 TCA9548A U22 Target Device Addresses
TCA9548A U22 (Addr 0x75) Port
0
1
2
3
4
5
6
7
For more information on the TCA9548A, TCA6416A, and PCA9544A, see the
website.
The detailed Zynq UltraScale+ RFSoC connections for the feature described in this section are
documented in the ZCU208 board XDC file, referenced in
UART0 (MIO 18-19)
[Figure 2, callout 8]
This is the primary Zynq UltraScale+ RFSoC PS-side UART interface and is connected to the FTDI
U29 FT4232HL USB-to-Quad-UART Bridge port B through TXS0108E level-shifter U32.
The FT4232HL U29 port assignments are listed in the following table.
Table 13: FT4232HL Port Assignments
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
I2C1 Bus Device
USER MGT Si570 Clock U48
8A34001 (zSFP ClK Recovery) U409
CLK104 Connector J101
RFMC LPAF-50 Connector J82
No Connection
I2C1 Bus Device
FMCP HSPC J28
USER Si570 C1 Clock U130
SYSMON U1 BANK 65
PS DDR4 SODIMM SKT. J48
SFP3 P3
SFP2 P2
SFP1 P1
SFP0 P0
FT4232HL U29
Port A JTAG
Port B UART0
Port C UART2
Port D UART3
Chapter 3: Board Component Descriptions
Target Device Address
0X5D
0x58
0x2F
USER
NA
Target Device Address
0x##
0X5D
0x32
0x51
0x50
0x50
0x50
0x50
Texas Instruments
Appendix B: Xilinx Design
Zynq UltraScale+ RFSoC U1
ZCU208 JTAG Chain
PS_UART0 (MIO 18-19)
PL_UART2 Bank 89
U38 System Controller UART
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Constraints.
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