Xilinx Zynq UltraScale+ ZCU208 User Manual page 7

• ZU48DR-2, FSVG1517 package
• Form factor: see
• Configuration from:
Dual QSPI
○
Micro-SD card
○
USB-to-JTAG bridge
○
PC4 2x7 2 mm JTAG pod flat cable header
○
• Clocks
GTR_REF_CLK_USB3 26 MHz
○
GTR_REF_CLK_SATA 125 MHz
○
CLK104 (various frequencies):
○
- CLK104_PL_CLK
- CLK104_PL_SYSREF
- CLK104_AMS_SYSREF
- CLK104_DDR_PLY_CAP_SYNC
- CLK104_ADC_REFCLK
- CLK104_DAC_REFCLK
8A34001 IEEE 1588, Synchronous Ethernet (SyncE), and eCPRI clock (various frequencies):
○
- 8A34001_Q1_OUT
- 8A34001_Q2_OUT
- 8A34001_Q3_OUT
- 8A34001_Q7_OUT
- 8A34001_Q8_OUT
- 8A34001_Q11_OUT
CLK_100 100 MHz
○
CLK_125 125 MHz
○
PS_REF_CLK 33.33 MHz
○
USER_MGT_SI570 (default 156.25 MHz)
○
USER_SI570_C0 (default 300 MHz)
○
USER_SI570_C1 (default 300 MHz)
○
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Board Specifications
Chapter 1: Introduction
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