Xilinx Zynq UltraScale+ ZCU208 User Manual page 41

Ethernet PHY LED Interface
[Figure 2, callout 16]
The DP83867IRPAP PHY U33 LED interface (LED_0, LED_2) uses the two LEDs embedded in
the P1 RJ45 connector bezel. The LED functional description is as shown in the following table.
Table 16: Ethernet PHY LED Functional Description
Pin
Name Number
LED_2 61
LED_1 62
LED_0 63
The LED functions can be re-purposed with a LEDCR1 register write available through the PHYs
management data interface, MDIO/MDC. LED_2 is assigned to ACT (activity indicator) and
LED_0 indicates link established.
LED_1 (100BASE-T link established) is a separate LED DS8 located on the top side of the board
near the RJ45 P1 connector
For more Ethernet PHY details, see the TI DS83867 data sheet on the
website.
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU208 board XDC file, referenced in
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Figure 14: Ethernet PHY Reset Circuit
Type
By default, this pin indicates receive or transmit activity.
Additional functionality is configurable by means of LEDCR1[11:8] register bits.
S, I/O, PD
Note: This pin is a strap configuration pin for RGZ devices only.
By default, this pin indicates that 100BASE-T link is established.
S, I/O, PD
Additional functionality is configurable by means of LEDCR1[7:4] register bits.
By default, this pin indicates that link is established.
S, I/O, PD
Additional functionality is configurable by means of LEDCR1[3:0] register bits.
(Figure 2, callout 16).
Appendix B: Xilinx Design
Chapter 3: Board Component Descriptions
Description
Texas Instruments
Constraints.
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