Xilinx Zynq UltraScale+ ZCU208 User Manual page 39

The USB3320 is clocked by a 24 MHz crystal (X2). See the
USB3320 data sheet for clocking mode details.
The interface to the USB3320 PHY is implemented through the IP in the ZU48DR RFSoC
Processor System (PS). USB OTG support is available for USB 2.0. See
settings.
Note: The shield for the USB 3.0 micro-B connector (J18) can be tied to GND by a jumper on header J20
pins 2-3 (default). The USB shield can optionally be connected through a series capacitor to GND by
installing a capacitor (body size 0402) at location C204 and jumping pins 1-2 on header J20.
The USB3320 ULPI U6 transceiver circuit (see the following figure) has a Micrel MIC2544 high-
side programmable current limit switch (U7). This switch has an open-drain output fault flag on
pin 2, which will turn on LED DS7 if overcurrent or thermal shutdown conditions are detected.
DS7 is located adjacent to the USB J18 connector
The following figure shows the ULPI U6 transceiver circuit.
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Figure 11: USB Interface
ULPI
USB
MIO
GTR Tx, Rx
USB
GTR
Figure 12: USB3320 ULPI USB 2.0 Transceiver Circuit
Chapter 3: Board Component Descriptions
SM3320
USB2.0
Connector
Standard Microsystems Corporation
Table 3
(Figure 2, callout 6).
Send Feedback
USB3
X23650-032720
for USB 2.0 jumper
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