Xilinx Zynq UltraScale+ ZCU208 User Manual page 40

The detailed RFSoC connections for the feature described in this section are documented in the
ZCU208 board XDC file, referenced in
GEM3 Ethernet (MIO 64-77)
[Figure 2, callout 16]
The PS-side Gigabit Ethernet MAC (GEM) implements a 10/100/1000 Mb/s Ethernet interface,
shown in the following figure, which connects to a TI DP83867IRPAP Ethernet RGMII PHY
before being routed to an RJ45 Ethernet connector. The RGMII Ethernet PHY is boot strapped to
PHY address 5'b01100 (0x0C) and Auto Negotiation set to Enable. Communication with the
device is covered in the TI DP83867 RGMII PHY data sheet on the
10/100/1000 MHz Tri-Speed Ethernet PHY
[Figure 2, callout 16]
The ZCU208 board uses the TI DP83867IRPAP Ethernet RGMII PHY (U33) (see
Instruments website) for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The
board supports RGMII mode only. The PHY connection to a user-provided Ethernet cable is
through a Wurth 7499111221A RJ-45 connector (P1) with built-in magnetics.
Ethernet PHY Reset
The DP83867IRPAP PHY U33 reset circuit is shown in the following figure. The DP83867IRPAP
can be reset by the GEN3_EXP_RESET_B signal through the I2C0 TCA6416A U15 bus expander
P06 pin 10 or the PS_POR_B signal generated by the MAX16025 U6 POR device pin 11.
SW4 pushbutton at the MAX16025 U5 pin 6 input also triggers a PS_POR_B signal.
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Appendix B: Xilinx Design
Figure 13: Ethernet Block Diagram
RGMII
GEM
MIO
MDIO
Chapter 3: Board Component Descriptions
Constraints.
Texas Instruments
RJ45 and
TI
Magnetics
DP83867IR
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