Xilinx Zynq UltraScale+ ZCU208 User Manual page 53

FMCP HSPC
Eight MGTs are provided by PL-side MGT banks 130 and 131. Available MGT reference clocks
include the FMC defined GBT clocks 0 and 1, a programmable SI570 clock and a differential SMA
clock.
zSFP+
Four MGTs are provided by PL-side MGT banks 128 and 129 for the quad (2x2 connector) zSFP+
interface. Available GTY reference clocks include two sets of clocks to/from IDT 8A34001 U409.
Each zSFP+ connector provides an I2C based control interface. This I2C interface is accessible for
each individual zSFP+ module through the I2C multiplexer topology on the ZCU208.
For additional information on GTY transceivers, see the UltraScale Architecture GTY Transceivers
User Guide (UG578).
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU208 board XDC file, referenced in
PS GTR Transceivers
The PS-side GTR transceiver Bank 505 supports USB (3.0) and SATA, with two channels not
used.
Bank 505 USB0 lane 2 supports the USB0 (USB3.0) interface documented in the USB 3.0
Transceiver and USB 2.0 ULPI PHY section. The PS-Side GTR transceiver is used to provide USB
3.0 Host-Only connectivity.
Bank 505 SATA lane 3 supports SATA connector U36 shown in
Bank 505 reference clocks are connected to the U43 SI5341B clock generator as described in
SI5341B 10 Independent Output Any-Frequency Clock Generator
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU208 board XDC file, referenced in
PS M.2 SATA Connector
[Figure 2, callout 31 and 32]
The M.2 SATA interface is provided for SATA SSD access using the PS-side bank 505 GTR
transceiver. The following figure shows the M.2 connector U36.
The socket 2 SATA adapter pinout with key M is shown in the table below. The SATA-A data
connection is used for TX and the SATA-B data connection is used for RX. The M.2 connector
U36 is a type 2242 (active component section 22 mm wide with overall length 42 mm form
factor) used on socket 2.
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Chapter 3: Board Component Descriptions
Appendix B: Xilinx Design
Appendix B: Xilinx Design
Constraints.
Figure 18.
U43.
Constraints.
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