Xilinx Zynq UltraScale+ ZCU208 User Manual page 26

PL C0 I/F DDR4 Component Memory
[Figure 2, callout 3]
The 4 GB, 32-bit wide DDR4 memory system is comprised of four 1 Gb x 8 SDRAM (Micron
MT40A1G8SA-075), U96-U99. This memory system is connected to PL-side ZU48DR banks 64
and 65. The DDR4 0.6V PL_DDR4_C0_VTT termination voltage is supplied from IR3897 sink-
source regulator U79.
• Manufacturer: Micron
• Part Number: MT40A1G8SA-075
• Description:
8 Gb (1 Gb x 8)
○
1.2V 78-ball FBGA
○
DDR4-2666
○
The ZCU208 ZU48DR RFSoC PL DDR interface performance is documented in the Zynq
UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
The ZCU208 board DDR4 32-bit component memory interface adheres to the constraints
guidelines documented in the PCB guidelines for DDR4 section of UltraScale Architecture PCB
Design User Guide (UG583). The ZCU208 DDR4 component interface is a 40Ω impedance
implementation. Other memory interface details are also available in the UltraScale Architecture-
Based FPGAs Memory IP LogiCORE IP Product Guide (PG150).
For additional details, see the Micron MT40A1G8SA-075 data sheet on the
website.
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU208 board XDC file, referenced in
PL C1 I/F DDR4 Component Memory
[Figure 2, callout 4]
The 4 GB, 32-bit wide DDR4 memory system is comprised of four 1 Gb x 8 SDRAM (Micron
MT40A1G8SA-075), U100-U103. This memory system is connected to PL-side ZU48DR banks
68 and 69. The DDR4 0.6V PL_DDR4_C1_VTT termination voltage is supplied from IR3897 sink-
source regulator U80.
• Manufacturer: Micron
• Part Number: MT40A1G8SA-075
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Chapter 3: Board Component Descriptions
Appendix B: Xilinx Design
Micron Technology
Constraints.
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