Xilinx Zynq UltraScale+ ZCU208 User Manual page 56

Table 24: M.2 U40 Connections to the XCZU48DR Zynq UltraScale+ RFSoC
XCZU48DR (U1) Pin
AD36
AD37
AC38
AC39
Notes:
1. Series capacitor coupled, MGT I/F and I/O standards do not apply.
For more information, see PCI_Express_M.2_Specification_Rev1.1_TS_12092016_NCB on the
PCI-SIG website.
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU208 board XDC file, referenced in
FPGA Mezzanine Card Interface
The ZCU208 evaluation board supports the VITA 57.4 FPGA mezzanine card plus (FMC+ or
FMCP) specification by providing a subset implementation of the high pin count connector at J28
(HSPC). FMC+ connectors use a 14 x 40 form factor, populated with 560 pins. The connector is
keyed so that a mezzanine card, when installed on the ZCU208 evaluation board, faces away
from the board.
FMCP Connector J28
Samtec SEAF series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector. More
information about SEAF series connectors is available on the
information about the VITA 57.4 FMC+ specification is available on the
Alliance website.
The 560-pin FMC+ connector defined by the FMC specification (see
FMCP Connector
• 160 single-ended or 80 differential user-defined signals
• 24 transceiver differential pairs
• 6 transceiver differential clocks
• 4 differential clocks
• 239 ground and 19 power connections
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Net Name
GT3_SATA1_TX_P
GT3_SATA1_TX_N
GT3_SATA1_RX_P
GT3_SATA1_RX_N
Appendix B: Xilinx Design
Pinout) provides connectivity for up to:
Chapter 3: Board Component Descriptions
I/O Standard
Pin Number
1
1
1
1
Constraints.
Samtec, Inc.
Send Feedback
M.2 Connector U40
Pin Name
49 SATA-A+
47 SATA-A-
41 SATA-B+
43 SATA-B-
website. More
VITA FMC Marketing
Appendix A: VITA57.4
www.xilinx.com
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