Xilinx Zynq UltraScale+ ZCU208 User Manual page 52

Multi-Gigabit Transceivers
The ZU48DR Zynq UltraScale+ RFSoC has 4 GTR gigabit transceivers (6 Gb/s capable) on the PS-
side and 16 GTY gigabit transceivers (28 Gb/s capable) on the PL-side. Two of four GTR
transceivers are used. All 16 GTY transceivers are used.
GTY Transceivers
The GTY transceivers in the ZU48DR are grouped into four channels or quads. The reference
clock for a quad can be sourced from the quad above or the quad below the GTY quad of
interest. The 4 GTY quads used on the ZCU208 board have the connectivity listed below. The
following table shows the MGTY assignments.
Table 21: ZCU208 ZU48DR GTY Mapping
ZU48DR-FSVG1517
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
ZCU208 ZU48DR-FSVG1517 GTY Mapping
8A34001 CLK1_IN - Q1_OUT
NO CONNECT
zSFP1
zSFP0
8A34001 Q11_OUT
8A34001 CLK5_IN
CoreHC2 1x8 Connector
NO CONNECT
zSFP3
zSFP2
8A34001 Q7_OUT
8A34001 CLK6_IN
FMC DP3
FMC DP2
FMC DP1
FMC DP0
USER_SMA_MGT_CLOCK
FMC GBTCLK0 M2C
FMC DP7
FMC DP6
FMC DP5
FMC DP4
USER_MGT_SI570_CLOCK
FMC GBTCLK1 M2C
Chapter 3: Board Component Descriptions
ch3
ch2
ch1
GTY Quad 128
ch0
refclk1
refclk0
ch3
ch2
ch1
GTY Quad 129
ch0
refclk1
refclk0
ch3
ch2
ch1
GTY Quad 130
ch0
refclk1
refclk0
ch3
ch2
ch1
GTY Quad 131
ch0
refclk1
refclk0
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