Xilinx Zynq UltraScale+ ZCU208 User Manual page 43

Clock Generation
The ZCU208 board provides fixed and variable clock sources for the ZU48DR Zynq UltraScale+
RFSoC. The following table lists the source devices for each clock.
Table 17: ZCU208 Board Clock Sources
Clock (Net) Name
Fixed Frequency Clocks
PS_REF_CLK
CLK_100
CLK_125
GTR_REF_CLK_SATA
GTR_REF_CLK_USB3
Programmable Frequency Clocks
USER_SI570_C0
USER_SI570_C1
USER_MGT_SI570_CLOCK
USER_SMA_MGT_CLOCK
Various 8A34001 eCPRI Clocks
The following table lists the connections for each clock.
Table 18: Clock Connections to ZU48DR U1
Clock Source Ref. Des. and Pin
U43 SI5341B Clock Generator
U43.59
U43.45
U43.44
U43.42
U43.41
U43.35
U43.34
U43.31
U43.30
U47 SI570 I2C Prog. Oscillator DDR4 C0 I/F (300 MHz default)
U47.4
U47.5
U130 SI570 I2C Prog. Oscillator DDR4 C1 I/F (300 MHz default)
U130.4
U130.5
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Chapter 3: Board Component Descriptions
Frequency
33.33 MHz
100 MHz
125 MHz
125 MHz
26 MHz
300 MHz (Default)
300 MHz (Default)
156.25 MHz (Default)
User-Provided Source
Various
Net Name
PS_REF_CLK (series R300)
CLK_125_P
CLK_125_N
CLK_100_P
CLK_100_N
GTR_REF_CLK_SATA_P
GTR_REF_CLK_SATA_N
GTR_REF_CLK_USB3_P
GTR_REF_CLK_USB3_N
USER_SI570_C0_P
USER_SI570_C0_N
USER_SI570_C1_P
USER_SI570_C1_N
Clock Source
U43 SI5341B Clock Generator (0x76)
U47 SI570 I2C PROG. OSC. (0x5D)
U130 SI570 I2C PROG. OSC. (0x5D)
U48 SI570 I2C PROG. OSC. (0x5D)
J6 (P)/J7 (N) SMA CONN.
U409 8A34001 (0x58)
I/O Standard ZU48DR (U1) Pin
1 U32
LVDS A13
LVDS A12
LVDS G12
LVDS G11
2 AB34
2 AB35
2 AC36
2 AC37
LVDS AR20
LVDS AR19
LVDS G17
LVDS
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