Xilinx Zynq UltraScale+ ZCU208 User Manual page 27

• Description:
8 Gb (1 Gb x 8)
○
1.2V 78-ball FBGA
○
DDR4-2666
○
The ZCU208 ZU48DR RFSoC PL DDR interface performance is documented in the Zynq
UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
The ZCU208 board DDR4 32-bit component memory interface adheres to the constraints
guidelines documented in the PCB guidelines for DDR4 section of UltraScale Architecture PCB
Design User Guide (UG583). The ZCU208 DDR4 component interface is a 40Ω impedance
implementation. Other memory interface details are also available in the UltraScale Architecture-
Based FPGAs Memory IP LogiCORE IP Product Guide (PG150).
For additional details, see the Micron MT40A1G8SA-075 data sheet on the
website.
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU208 board XDC file, referenced in
PSMIO
The following table provides PS MIO peripheral mapping implemented on the ZCU208 board.
See the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for more information on PS
MIO peripheral mapping.
Table 7: MIO Peripheral Mapping
MIO[0:25] Bank 500
0 QSPI_LWR
1 QSPI_LWR
2 QSPI_LWR
3 QSPI_LWR
4 QSPI_LWR
5 QSPI_LWR
6 Not assigned/no connect
7 QSPI_UPR
8 QSPI_UPR
9 QSPI_UPR
10 QSPI_UPR
11 QSPI_UPR
12 QSPI_UPR
13
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Appendix B: Xilinx Design
MIO[26:51] Bank 501
26
27
28
29
30
31
32
33
34
35
36
37
38
GPIO 39
Chapter 3: Board Component Descriptions
PMU IN
Not assigned/no connect
Not assigned/no connect
Not assigned/no connect
Not assigned/no connect
Not assigned/no connect
PMU GPO
PMU GPO
PMU GPO
PMU GPO
PMU GPO
PMU GPO
GPIO
SD1
Send Feedback
Micron Technology
Constraints.
MIO[52:77] Bank 502
52 USB0
53 USB0
54 USB0
55 USB0
56 USB0
57 USB0
58 USB0
59 USB0
60 USB0
61 USB0
62 USB0
63 USB0
64 GEM3
65 GEM3
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