Digital Equipment DEC 3000 Series Service Information page 19

System Overview,
CPU/Cache
Continued
The DEC 3000 Model 500/500S AXP system contains a single chip
processor and floating point running at 6.6ns. The processor is a
superscalar, superimplementation of the Alpha AXP architecture.
The DEC 3000 Model 500/500S AXP system contains the following
direct-mapped caches:

Icache (instruction cache)

Dcache (data cache)
The system uses a second-level cache to help minimize the
performance penalty of misses and write-throughs to the primary
cache. This second-level cache is a 512K byte, direct-mapped,
write-back cache with a block size of 32 bytes.
The cache is implemented on the system module using 32K byte
2
8 static RAMs. Theread bandwidth between the processor and
the second level cache is approximately 640 MB/s, and the write
bandwidth is 420 MB/s.
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