Iic Fan Controller And Temperature Monitor; Configuration Options; Jtag (Parallel Cable Iv Cable And System Ace Controller) - Xilinx ML405 User Manual

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39. IIC Fan Controller and Temperature Monitor

The board contains an IIC controlled fan controller chip and fan connector. The Maxim
MAX6653 fan controller (U66) contains on-chip and remote temperature monitors. The
on-chip temperature measures the ambient temperature near the surface of the board. The
remote temperature monitoring pins are connected to the FPGA TDP/TDN pins that
access a temperature diode in the FPGA.
The MAX6653 also offers other features such as fan speed control, tachometer, and
programmable speed control based on temperature trip points.
Connector J51 is a keyed three-pin fan header similar to those found in PCs. It is designed
to support a 5V DC fan. To bypass the fan controller chip and operate the fan at full speed,
the user can populate connector J50.
For high-power operating conditions, a heatsink and/or fan can be accommodated on the
board. The ML405 does not ship with a heatsink/fan unit but can accommodate one (for
example, Calgreg Electronics Smart-CLIP family of heatsink/fan assemblies).

Configuration Options

The FPGA on the ML405 evaluation platform can be configured by four major devices:
•
•
•
•
The following section provides an overview of the possible ways the board can be
configured.

JTAG (Parallel Cable IV Cable and System ACE Controller)

The FPGA, Platform Flash memory, and CPLD can be configured through the JTAG port.
The JTAG chain of the board is illustrated in
The chain starts at the PC4 connector and goes through the System ACE controller, the
Platform Flash memory, the FPGA, the CPLD, and an optional extension of the chain to the
expansion card. Jumper J26 determines if the JTAG chain should be extended to the
expansion card.
The JTAG chain can be used to program the FPGA and access the FPGA for hardware and
software debug. The JTAG chain is also used to program the Platform Flash memory and
the CPLD.
ML405 Evaluation Platform
UG210 (v1.5.1) March 10, 2008
Parallel Cable IV or other download cable (JTAG)
System ACE controller (JTAG)
Platform Flash memory
Linear flash + CPLD
System ACE
Controller
TSTTDI CFGTDO
TSTDO CFGTDI
www.xilinx.com
Figure 1-5.
Platform Flash
FPGA
Memory
TDI TDO TDI TDO
Figure 1-5: JTAG Chain
Configuration Options
Expansion
CPLD Card
TDI TDO TDI
TDO
UG080_05_061506
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