Extracting The Project Files - Xilinx Virtex-7 FPGA VC7215 Getting Started Manual

Extracting the Project Files

The Vivado project files required to run the IBERT demonstrations are located in
rdf0294-vc7215-ibert-2014-4.zip on the SD card provided with the VC7215
board. They are also available online at the
website.
The ZIP file contains these files:
•
•
•
•
The Tcl scripts are used to help merge the IBERT and SuperClock-2 source code (described
in
325.00 MHz (described in
To copy the files from the Secure Digital memory card:
1.
2.
3.
VC7215 Getting Started Guide
UG970 (v7.0) November 24, 2014
BIT files
• 20 BIT files, one for each of the board's 20 Quads
(vc7215_ibert_qxxx_325.bit)
Probe files
• 20 probe files, one for each of the board's 20 QuadS (vc7215_qxxx_325.ltx)
The complete project files
TCL scripts
• add_scm2.tcl
• setup_scm2_325_00.tcl
Creating the GTH IBERT Core, page
Setting Up Vivado Design Suite, page
Connect the Secure Digital memory card labeled IBERT #1 to the host computer.
Locate the file rdf0294-vc7215-ibert-2014-4.zip on the Secure Digital
memory card.
Unzip the files to a working directory on the host computer.
www.xilinx.com
Extracting the Project Files
Virtex-7 FPGA VC7215 Characterization Kit
27) and to set up the SuperClock-2 module to run at
15).
7
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