Registers Controlling Low-Voltage Detector - NEC 78K0S/KA1+ User Manual

16.3 Registers Controlling Low-Voltage Detector

The low-voltage detector is controlled by the following registers.
• Low-voltage detect register (LVIM)
• Low-voltage detection level select register (LVIS)
(1) Low-voltage detect register (LVIM)
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input clears this register to 00H
Address: FF50H After reset: 00H
<7>
Symbol
LVION
LVIM
Note 3
LVION
0 Disable operation
1 Enable operation
LVIMD
0 Generate interrupt signal when supply voltage (V
1 Generate internal reset signal when supply voltage (V
Note 4
LVIF
0 Supply voltage (V
1 Supply voltage (V
Notes 1. For a reset by LVI, the value of LVIM is not initialized.
2. Bit 0 is a read-only bit.
3. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use
software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is
confirmed at LVIF.
4. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and
LVIMD = 0.
Cautions 1. To stop LVI, follow either of the procedures below.
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
2. Be sure to set bits 2 to 6 to 0.
250
CHAPTER 16 LOW-VOLTAGE DETECTOR
Note 1
.
Figure 16-2. Format of Low-Voltage Detect Register (LVIM)
Note 1 Note 2
R/W
6 5 4
0 0 0
Enabling low-voltage detection operation
Low-voltage detection operation mode selection
Low-voltage detection flag
) ≥ detection voltage (V
DD
) < detection voltage (V
DD
User's Manual U16898EJ3V0UD
3 2 <1>
0 0 LVIMD
) < detection voltage (V
DD
) < detection voltage (V
DD
), or when operation is disabled
LVI
)
LVI
<0>
LVIF
)
LVI
)
LVI