Interruptstructure - Intel MCS 51 User Manual

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83C152 HARDWARE DESCRIPTION
2.2
Interrupt Structure
interrupts and IPN1 (F8H) for settingthe priority.For
an explanationon how the priority of interrupts affects
The C152retains all fiveinterruptsof the 80C51BH. I n
their operationpleasereferto the MCS-51Architecture
additiorLsix new interrupts havebeenadded for a total
and Hardware Chapters io the Intel EmbeddedCon-
of 11available interrupts. Two SFRShave beerradded
troller Handbook.A detailed description on how the
to the C152 for control of the new interrupta. These
interrupts function is in the MC$W51 Architectural
added SFRS are IEN1 (C8H) for enabling the
Overview.
I
IEN1 FUNCTIONS
I
Symbol
I
Position Vector Function
—
IFN1 7
I I
RFGFBVFn sm~do not e~st on chip.
I
I
.-. . . . .
I
1
------- . -- -..
——-——. .——
N1.6 i I RESERVED
anddonotexist n n~hin
I
—
IEI -. ".. -...~.
EGSTE IEN1.5 04BH
GSC
TRANSMIT ERROR-Theinterrupt service routine a t
4BHisinvoked if NOACK orTCDTisset
when the GSC is
I
I I I
under C PUcontrol andEGSTE isenabled. Thisinterrupt
service routine isinvoked ifNOACK, TCDT,orURissetwhen
I
the GSC is
under D MAcontrol andEGSTE isenabled.
EDMA1 IEN1.4 053H DMACHANNEL REQUEST l-The interrupt service routine
EGSTV IEN1.3
EDMAO IEN1.2
043H
03BH
at 53H is invokedwhen DCON1.1 (DONE) is set and EDMA1
is enabled.
GSC TRANSMIT VALID-lTre
interruptservice
routineat 43H
is invokedifTFNF is set whenthe GSC is under
CPUcontrol
andEGSTV isenabled. Thisinterrupt service routine is
invoked if
TDN isset whenthe GSC is underDMA controland
EGSTV is enabled.
DMA CHANNEL REQUEST (+The interruptserviceroutine
at 3BH willbe invokedwhen DCONO.1(DONE) is sat and
EDMAOis enabled.
EGSRE
EGSRV
IEN1.1
IEN1.O
033H
02BH
GSC RECEIVE ERROR-The interruptserviceroutineat 33H
is invokedif CRCE, OVR, RCABT,or AE is set when the GSC
is underCPU or DMA controland EGSRE is enabled.
GSC RECEIVE VALID-The interruptseMce routineat 2BH
is invokedif RFNE is set whenthe GSC is underCPU control
and EGSRV is enabled.This interruptserviceroutineis
invokedif RDN is set when the GSC is underDMA controland
EGSRV
is
enabled.
IPN1 is used the same way the current 80C51BHinterrupt priority register (1P) is. By assigninga "l" to the
approptite bit, thst interrupt has a higherpriority than an interrupt with a "O"assignedto it in the priorityregister.
The new interrupt priority register(IPN1) contents are:
Symbol Position
Function
PGSTE IPN1.5 GSCTRANSMIT ERROR
PDMA1 IPN1.4 DMA CHANNELREQUEST 1
,
I
PGSTV
IPN1.3 GSCTRANSMITVALID
PDMAO
IPN1.2 DMA CHANNELREQUEST O
PGSRE IPN1.1 GSC RECEIVEERROR
PGSRV
IPN1.O
GSC RECEIVEVALID
7-11