Programmable Clock Out; Uart; Framing Error Detection; Automatic Address Recognitino - Intel MCS 51 User Manual

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8XC52/54/58
HARDWARE DESCRIPTION
The Timer can be configured for either "timer" or
"counter" operation. In most apj&ations, it is contlg-
ured for "timer"operation (CP/T2 = O).The "timer"
operation is different for Timer 2 when it's being used
es a baud rategenerator. Normally, as a timer, it incre-
ments every machine cycle (thus at 1/lz the oscillator
frequency). As a baud rate generator,however, it incre-
ments every state time (thus at 1/2the oscillator fre-
quency). The baud rate formula is given below:
Modes 1 and3 =
Oscillator
Frequency
Baud Rate
32X [65536 – (RCAP2H,
RCAP2L)1
where (RCAP2H, RCAP2L) is the content of
RCAP2H end RCAP2L takemas a 16-bit unsigned in-
teger.
Timer 2 es a baud rate gemerstoris shown in Figure 5.
This figure is valid only if RCLK or TCLK = 1 in
T2CON. Note that a rollover in TH2 does not set TF2,
and will not generate an interrupt. Note too, that if
EXEN2 is se~ a l-to-O transition in T2EX will set
EXF2 but will not cause a reload from (RCAP2H,
RCAP2L) to ('fH2, TL2). Thus when Timer 2 is in use
as a baud rategenerator, T2EX can be used as an extra
exte.mal interrupt,if desired.
It should be noted that when Timer 2 is running (TM
= 1) in "tinter" fintction in the baud rate generator
mode, one should not try to read or write TH2 or TL2.
Under these conditions the Timer is being incremented
every state time, end the results of a reed or write may
not be accurate.The RCAP2 registersmaybe remLbut
shouldn't be written to, because a write might overlap a
reload end cause write end/or reload errora.The timer
should be turned off (clear TR2) before accessing the
Timer 2 or RCAP2 registers.
PROGRAMMABLE CLOCK OUT
A 50% duty cycle clock can be programmed to come
out on P1.O.This pim besides being a regular1/0 pin,
has two alternatetimctions. It can be programmed (1)
to input the external clock for Timer/Counter 2 or (2)
to output a 50~0 duty cycle clock ranging from 61 Hz
to
4 MHz at a 16 MHz operating frequency.
To configurethe Timer/Counter 2 as a clock generator,
bit C/T.2 (T2CON.1) must be cleared and bit T20E
(T2MOD.1) must be set. Bit TR2 (T2CON.2) starts
and stops the timer.
The Clock-Out frequencydepends on the oscillator fre-
quency and the reload value of Timer 2 capture regis-
ters (RCAP2H, TCAP2L) as shown in this equation:
Clock-Out Frequency =
Oscillator Frequency
4 X (65536 - RCAP2ti, RC2AP2L)
In the clock-out mode, Timer 2 roll-overs will not gen-
erate an interrupt. This is similar to when Timer 2 is
used as a baud-rate generator.It is possible to use Tim-
er 2 as a baud-rate generator and a clock generator
simultaneously. Note, however, that the baud-rate and
ermined indepen-
clock-out frequencies can not be det
dently from one another since they both use RCAP2H
and RCAP2L.
UART
The
UART in the 8XC5X operates identically to the
UART in the 80C51 except for the following enhsnce-
menta. For a complete understanding of the 8XC5X
UART please refer to the description in the 30C51
Hardware Description chapter in the Embedded Mi-
crocontroller's and ProcessorsHandbook.
Franting Error Detection-Framin g Error Detection
allows the serial port to check for valid stop bits in
modes 1, 2 or 3. A missing stop bit can be caused for
example, by noise on the seriallinesj or transmission by
two CPUS simultaneously.
If a stop bit is missing a Framing Error bit (FE) is set.
The FE bit can be checked in softwsre after each recep-
tion to detect communication errors. Once set, the FE
bit must be cleared in sotlwsre. A valid stop bit will not
clear FE.
The FE bit is located in SCON and shares the same bit
addreesas SMO.Control bit SMODOin the PCON reg-
ister (location PCON.6) determines whether the SMO
or FE bit is amessed. If SMODO = O,then mcesaes to
SCON.7 are to SMO.If SMODO = 1, then -ses to
SCON.7 are to FE.
Automatic Address R eeognition-Autornatic
Address
Recognition reduces the CPU time required to service
theserialport.SincetheCPUisonlyinterrupted when
it receives its own address, the software overhead to
compare addresses is eliminated. With this
feature en-
abled in one of the 9-bit modes, the Receive Interrupt
(RI) tlag will only get set when the received byte corre-
sponds to either a Oiven or Broadcast address.
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