Intel MCS 51 User Manual page 201

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8XC51FXHARDWARE DESCRIPTION
The other way of terrnina ting the Idle mode is with a The signal at the RST pin clears the IDL bit directly
hardware reset. Since the clock oscillator is still nm- snd asynchronously. At this time the CPU resumes
ning, the hardwarereset needs to be held active for only program execution from where it left off; that is, at the
two machine cycles (24 oscillator periods) to complete instruction following the one that invoked the Idle
the reset. Mode. As shown in Figure 26, two or three machine
cycles of program execution may take place before the
II 2'7
T
STAL 2 = xTAL1
1
I
Oac
+
%-l
I
CLOCS
INTERRUPT,
GEN.
1
DSERIAL PORT,
TIMER BLOCKS
Figure 28. Idle and Power Down Hardware
Table 23. PCON:Power Control ReQieter
PCON Address = 87H
Reset Value = OOXX OOOOB
Not Bit Addressable
SMOD1SMODO — POF GF1 GFO PD IDL I
Bit 7
6 5 4 3 2
1
0
Symbol Funotion
SMOD1
SMODO
—
POF
GF1
GFO
PD
IDL
NOTE
DoubleBaudratebit.Whensetto a 1 andTimer1 is usedto generate baudrates,andthe
SerialPortis usedin modes1,2, or 3.
Whenset,Read/Writeaccesses to SCON.7 areto the FEbit.Whenclear,Read/Write
accesses to SCON.7 areto the SMO bit.
Not implemented, reserved for futureuee.*
Power Off Flag. Set by hardware on the rising edge of VCC. Set or cleared by software. This
flag allows deteetion of a power failure caused reset. V= must remain above 3V to retain
this bit.
General-purpose flag bit.
General-purpose flagbit.
PowerDownbit.Settingthis bitactivatesPowerDownoperation.
Idlemodebit.Settingthisbit activates idlemodesoperation.
If 1sarewrittento PDandIDLat the sametime,PDtakesprecedence.
*Uaer softwareshouldnot write la to unimplemented bits.These bits msy be used in future8051 familyproductsto
invokenew featurea. In that ease, the reset or inactivevalue of the new tit will be O, and ifa active valus will be 1.
The vslueread from a reservedbit is indeterminate
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