Intel MCS 51 User Manual page 333

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83C152 HARDWARE DESCRIPTION
RSTAT.6(RCAB~ - ReceiverCollision/AbortDetect
- IfseL indicatesthat a collisionwasdetectedafter data
had been 10wM into the receiveFIFO in CSMA/CD
mode.In SDLCmodq RCABTindicatesthat 7 consec-
utive oneswere detected prior to the end tlag but after
data has keen loaded into the receiveFIFO. AE may
also be set if RCABT is set.
RSTAT.7(OVR) - Overrun - If set, indicatesthat the
receiveFIFO was full and new shift register data was
written into it. It is cleared by user software, AE
and/or CRCE may also be set ifOVR is set.
SARHO(OA3H)- Source Addreas Register High O,
containsthe high byte of the source address for DMA
ChannelO.
SARHI (OB3H)- Source Address Register High 1,
containsthe high byte of the sourceaddress for DMA
channel 1.
SARLO (OA2H)- SourceAddressRegisterLowO,con-
tains the low byte of the source address for DMA
ChannelO.
SARLI (OB2H) - SourceAddressRegisterLow 1,con-
tains the low byte of the source address for DMA
channel 1.
SAS- SourceAddress Spacebit, see DCONO.
SBUF (099H) - Serial Buffer, both the receive and
transmit SFR location for the LSC.
SCON(098H)
7 6 5 4 3210
SMO
SM1 SM2 REN
TB8 \ RB8 TI I RI
SCON.O(RI) -
ReceiveInterrupt fiag.
SCON.1(TI) - Transmit Interrupt tlag.
SCON.2(RB8) - ReceiveBit 8, containsthe ninth bit
that was receivedin Modes 2 and 3 or the stop bit in
Mode 1 if SM20.Not used in ModeO.
SCON.3
(TB8) -
Trrmsmit Bit 8, the ninth bit to be
transmitted in Modes 2 and 3.
SCON.4 (REm - Receiver Enable, enables reception
for the I-SC.
SCON.5(SM2)- Enablesthe multiprocessorcommuni-
cation feature in Modes 2 and 3 for the LSC.
SCON.6(SM1)- LSC mcde sptxirler.
SCON.7(SM2)- LSC mode speciiier.
SDLC- Standsfor SynchronousData Link Cmmmni-
cation and is a protocol developedby IBM.
SLOTTM- (OB4H)Determin es the length of the slot
time in CSMA/CD.
SP (081H)- Stack Pointer, an eight bit pointer register
used duringa PUSN POP, CALL, RET, or RETL
TCDCNT - (OD4H)Contains the numberof collisions
in the currcnt frame if using probabilisticCSMA/CD
and containsthe maximum number of slots in the de-
terministicmode.
TCDT - Transmit CollisionDetec~ see TSTAT.
TCON (088H)
76543210
TF1 TR1 TFo
TRO IE1 IT1 IEO ITO
TCON.O(ITO)- Interrupt Omode controlbit.
TCON.1(IEO)- External interrupt Oedgetlag.
TCON.2(ITl) - Interrupt 1 mode controlbit.
TCON.3(IEl) - External interrupt 1 edgeflag.
TCON.4(TRO)- Timer Orun control bit.
CON.5(TFO)- Timer Oovertlowflag.
TCON.6(TR1) - Timer 1 run control bit.
TCON.7(TF1) - Timer 1 over-tlow flag.
TDN - Transmit Done flag, w TSTAT.
TEN - Transmit Enable bit, see TSTAT.
TFNF - Transmit FIFO Not Full tlag, see TSTAT.
TFIFO - (85H) TFIFO is a 3-byteFIFO that contains
the transmissiondata for the GSC.
THO(08CH) - Timer O High byte contains the high
byte for timer/cmmter O.
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