Intel MCS 51 User Manual page 255

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87C51GB HARDWARE DESCRIPTION
Table24.InterruptPolling Sequence
1 (Highest) INTO
2
SEP
3
INT2
4 TimerO
5
PCAI
6
INT3
7
m
6
AfD
9 INT4
10
Timer1
11
PCA
12
INT5
13 PCA
14
Timer2
15 (Lowest)
INT6
Note that
the
"miority within level" structure is
OtdY
used
to
resolves-tiul~eous requestsof the sameprior-
ity level.
12.7 InterruptProcessing
The interrupt flags are sampled at S5P2 of every mac-
hine cycle. The samplesare polled during the follow-
ing machine cycle. The Timer 2 overflowinterrupt is
slightly dif%rent, ss described in the Interrupt Re-
sponse Time section. If one of the flags was in a set
condition at S5P2 of the preceding cycle+the polling
cycle will find it and the interrupt system will generate
so LCALLto the appropriateserviceroutine, provided
this hardwsre-generatedLCALLis not blockedby any
of the followingconditions:
1. An interrupt of equal or higher priority level is al-
resdy in progress.
2. The current (polling)cycle is not the final cycle in
the executionof the instructionin progress.
3. The instruction in progressis RETI or any write to
the IE or 1P registers.
Any of these three conditionswill block the generation
of the LCALL to the interrupt serviceroutine. Condi-
tion 2 ensures that the instruction in progress will be
completedbeforevect*g to any serviceroutine. Con-
dition 3 ensures that f the instruction in progress is
RETIor anywriteto IE or 1P,thenat leastonemore
instructionwillbe executedbeforeany interrupt is vec-
tored to.
The pollingcycle is repeatedwith each machine cycle,
and the valuespolledare the valuesthat were presentat
S5P2 of the previous machine cycle. If the interrupt
flag for a level-sensitive external interrupt is active but
not being respondedto for one of the aboveconditions
and is not still active when the blockingcondition is
removed the denied interrupt w ill not be serviced. In
other word$ the fact that the interrupt f&g was once
active but not servicedis not remembered.Every poll-
ing cycle is new.
T'hepollingcycle/LCALLsequenceis illustrated in the
Interrupt ResponseTimingDisgrarn.
Note that if an interrupt of a higher priority level goes
active prior to S5P2of the machinecyclelabeledC3 in
the diagram, then in accordancewith the aboverules it
will be vectoredto during C5 and C6, without any in-
struction of the lowerpriorityroutine havingbeen exe-
cuted. This is the fastest possibleresponse when C2 is
the tinal cycle of an instruction other than RETI or
write IE or 1P.
Thus the processoracknowledgesan interrupt request
by executinga hardware-generatedLCALLto the ap-
propriate servicing routine. The hardware-generated
LCALL pushes the contents of the Program Counter
onto the stack (but it does not save the PSW) and re-
loads the PC with an address that depends on the
source of the interrupt being vectored to. Table 25
shows the interrupt vectoraddresses.
Table25.InternmtVeotorAddresses
Interrupt Interrupt Clearedby Vector
Souroa Request B ite Hardware Addraae
m
IEO No(level) OO03H
Yes(trans.)
I TimerO I TFO I Yes I OOOBH !
m
IE1 No(level) O013H
Yes(trans.)
Timer1
TF1 Yes OOIBH
SerialPortI
Rl,TI
No O023H
Timer2
TF2,EXF2 No O02BH
SEP SEPIF
No O04BH
INT2 IE2 Yes
O053H
INT3 IE3
Yes O05BH
INT4
IE4 Yes
O063H
INT5
IE5 Yes
O06BH
I INT6 I
IE6
! Yes I O073H I
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