I/O Configurations; Writing To A Port - Intel MCS 51 User Manual

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HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
Port Pin Alternate Function
"P1.o T2
(Timer/Counter 2
external i nput)
*P1.1 T2EX(Timer/Counter 2
Capture/Reload trigger)
P3.O RXD (serialinputport)
P3.1
TXD (serialoutputport)
P3.2 INTO(externalinterrupt)
P3.3
~ (externalinterrupt)
P3.4
TO (Timer/CounterOexternal
input)
P3.5
T1 (Timer/Counter I external
input)
P3.6
~ (externalData Memory
write
strobe)
P3.7
~
(external DataMemory
readstrobe)
P1.Oand P1.1 serve these aftemate fuctions onlyon
the 8052.
The alternate functionscan onlybe activatedif the cor-
respondingbit latch in the pm-tSFR containsa 1.0th-
erwise the port pin is stuck at O.
1/0 Configurations
Figure 4 shows a fictional diagram of a typical bit
latch and 1/0 buffer in each of the four ports. The bit
latch (one bit its the port's SFR) is represented as a
Type D tlipflop, which will clock in a value from the
internal bus in response to a "write to latch" signal
from the CPU. The Q output of the tlipflop is placed
on the intersttdbus itsresponseto a "read latch" signal
from the CPU. The levelof the port pin itselfis placed
on the internal bus in response to a "read pin" signal
from the CPU. Someinstructionsthat read a port acti-
vate the "read latch" signal, and others activate the
"read pin" signal.More about that later.
As shownin Figure4, the output drivers of Ports Oand
2 are switchableto an istternrdADDR and ADDR/
DATA bus by an internal CONTROLsignalfor w its
external memoryaccesam. During external memoryac-
cesses,the P2 SFR rcsrm "nsunchanged,but the POSFR
gets 1s written to it.
Nso shownin Figure4, is that ifa P3 bit latch contains
a 1, then the output level is controlled by the signal
labeled "alternate output function." The actual P3.X
pin levelis afwaysavailableto the pin'salternate input
function, if any.
Ports 1,2, and 3 have internal puUups. P ort Ohas open
drain outputs.Each I/O line ean be independentlyused
as an input or an output. (Ports O and 2 may not be
used as general purpose I/O whetsbeing used as the
ADDIVDATA BUS).To be usedas an input, the port
bit latch must contain a 1, which turns off the output
driver FBT. Then, for Ports 1, 2, and 3, the pin is
pulled high by the internal puflup,but can be pulfed
low by an external source.
Port Odiffersin not havinginternsdpullups.The ptiup
FBT in the POoutput driver (seeFigure4) is used onfy
when the Port is ernitdng 1s during external memory
accasea otherwise the pullupFET is off. Conaequent-
Iy POlima that are being used as output port lines are
open drain. Writing a 1 to the bit latch leaves both
output FETs off, so the pin floats. In that conditionit
can be used a high-impedance input.
BecausePorts 1, 2, and 3 have fixed internaf pullups
they are sometimescalled "qussi-bidirectional"porta.
Whets eontigured as inputs they pull high and will
sourcecurrent (IIL, in the data sheets)whenextemafly
pulled low. Port O, on the other hand, is considered
"true" bidirectional,becausewheneont@red as an in-
put it floats.
Affthe port latches itsthe 8051have 1swritten to them
by the reset function.If a Ois subsequentlywritten to a
port latch, it can be reconfiguredas an input by writing
a 1 to it.
Writingto a Port
In the executionof an instructionthat changesthe val-
ue in a port latch, the new value arrives at the latch
during S6P2of the final cycleof the instruction. How-
ever, port latches are in fact sampledby their output
buffers
O~Y
during Phase 1 of SSly clock period. @IK-
ittg Phase 2 the output buffer holds the value it saw
during the previous Phase 1). Consequently,the new
value in the port latch won't actually appear at the
output pin until the next Phase 1,whichwillbe at SIP1
of the next machinecycle.SeeFigure39in the Internal
Timingsection.
If the changerequiresa O-to-1 transitionin Port 1,2, or
3, art additional pullup is turned on during SIP1 and
S1P2of the cyclein whichthe transitionocmu-s.. This is
done to increasethe transition speed.The extra pullup
can sourceabout 100timesthe current that the normal
pullup can. It shouldbe noted that the internal pttllups
are field-effect t ransistors, not linear resistors.Tlseptdl-
up
-CInCntS are
shownin Figure 5.
In HMOS veraionsof the 8051,the fixed part of the
pullup is a depletion-modetransistor with the gate
wiredto the source.This transistorwillallowthe pin
to
source about 0.25 mA when shorted to ground. In
parallel with the fixed pullupis assenhancement-mode
transistor, which is activated during S1 wheneverthe
port bit doesa O-to-1transition.Duringthis intervaf,if
the port pin is shorted to ground,this extra transistor
will allowthe pin to sourcean additional30 sttA.
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