Intel MCS 51 User Manual page 217

i~.
87C51GB HARDWARE DESCRIPTION
remains unchanged,
but the POSF'Rgets 1s written to
it.
If a PI through P5 latch containsa 1, then the output
level is controlledby the signal labeled"alternate out-
put function." The pin level is alwaysavailableto the
pin'salternate input function,if any.
Ports 1 through 5 have internal pullupa. Port O has
opendrain outputs.Each 1/0 line canbe independently
usedas an input or an output (Ports Oand 2 maynot be
used as general purpose 3/0 when being used as the
ADDRBWDATA BUS).To be used as an inpuLthe
port bit latch must contain a 1, which turns off the
output driver PET. On Ports I through 5 the pin is
pulled high by the internal pullup, but can be pulled
low by an external source.
PI, P2, P4, and P5 reset to a low state. Whilein reset
these pins can sink large amounts of current. If these
ports are to be used as inputs and externally driven
high whilein reset, the user shouldbe awareof possible
contention.A simple solution is to use open collector
interfaces with these port pins or to bufferthe inputs.
Port Odiffersfrom the other ports in not havinginter-
nal puliups.The pullup FET in the POoutput driver is
used only whenthe port is emitting 1sduring external
memory acceses. otherwise the pullup FET is off.
ConsequentlyPO lines that are being used as output
port lines are open drain. Writing a 1 to the bit latch
leavesboth output FBTs off, which floats the pin and
allowsit to be usedas a high-impedance input. Because
Ports 1 through 5 have freed internal pullupsthey are
sometirneacalled "quasi-bidirectional"porta.
When configured as inputs they pull high and will
source current (IIL in the data sheets) whenexternally
pulled low. Port O, on the other hand, is considered
"true" bidirectional,because it floats when configured
as an input.
The latchesfor ports Oand 3 have 1swrittento them by
the reset function. If a O is subsequentlywritten to a
port latch, it can be reconfiguredas an input by writing
a 1 to it.
4.2 Writing to a Port
In theexecution ofaninstruction thatchangea theval-
uein a portlatch,thenewvalue arrives at thelatch
during State 6,Phase 2 ofthefti cycle oftheinstruc-
tion. Howewr, port latch= are sampledby their output
bufkrs only during Phase 1 of any clockperiod. (Dur-
ing Phase 2 the output buffer holds the value it saw
during the previousPhase 1). Consequently,the new
value in the port latch won't actually appear at the
output pin un~ilthe next Phaac 1,which~ be at SIPI
of the next machinecycle. Refer to Figure 3.
SIAIE4 STA7E . 5 STATE 6 SIAIE1 STATE 2 SIAIE3 STATE 4 STATE 5
lPllmlmlmlmlnlPl lnlml*Imlmlmlml Pllml
XTAL1:
VI-. PO. P1, P Z, P S, P 4, P 6 PO, P1, P Z, P 3. P 4, P 6
wu?a aAnPLEo:
=
Uov
PORT, SRC: OLO OATA
I
NEW
OATA
iiiEF~ +
+RXDPINSANIUO
RXOSAMPUO+ k-
270S97-5
Figure3. PortOperation
6-9