Intel MCS 51 User Manual page 300

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83C152 HARDWARE DESCRIPTION
DMA channels the source or destination of the data
intended for serial transmission can be internal data
memory,externaldata memory,or any of the SFRS.
The onlytasks requiredafter initializationof the DMA
and GSC registers are enabling the proper interrupts
and informingthe DMA controllerwhento start. After
the DMA channelsare started affthat is requiredof the
CPU is to respondto error conditionsor wait until the
end of transmission.
Initializationof the DMA channelsrequires settingup
the control, source, and destination address registers.
On the DMA channel servicingthe receiver, the con-
trol registerneedsto be loadedas folfows:DCONn.2=
O,this sets the transfer modeso that responseis to GSC
interrupts and put the DMA control in alternate cycle
modq DCONn.3 = 1, this enablesthe demandmode;
DCONn.4 = O, this clears the automatic increment
optionfor the sourceaddres$ and DCONn.5 = 1,this
detbes the sourceas SFR.The DMA channelservicing
the receiver also needs its source address register to
contain the addreas of RFIFO (SARHN = XXII,
SARLN = OF4H). O n the DMA channelservicingthe
transmitter, the control register needs to be loaded as
follows:DCONn.2 = O;DCONn.3 = 1;DCONn.6=
O, this clears the automatic increment option for the
destinationaddress; and DCONn.7 = 1, this sets the
destination as SFR. The DMA channel serving the
transmitter also requirea that its destination address
register contains the address of TFIFO (DARHN =
XXI-I, DARLN = 85H). Assuming that DCONO
would be servingthe receiver and DCON1 the trans-
mitter, DCONOwould be loaded with XX101OXOB
and DCON1 wouldbe loaded with 10XX1OXOB. The
contents of SARHOand DARH1 do not have any im-
pact whenusinginternal SFRSas the sourceor destina-
tion.
Whenusingthe DMA channelsto seMce the GSC,the
byte count registerswill also need to be initialized.
The Done flag for the DMA channel servicingthe re-
ceiver should be used if fixed packet lengths only are
beingtransmittedor to insure that memoryis not over-
written by long receiveddata packets. Ovenvritingof
data can occur when using a smaller buffer than the
packet size. In these cases the servicingof the DMA
and/or GSC wouldbe in responseto the DMA Done
flag when the byte count reaches zero.
In some cases the bufk size is not the limitingfactor
and the packet lengthswill be unknown.In these cases
it would be desirableto eliminate the functionof the
Done tlag. To effectivelydisable the Done tlag for the
DMA channel servicingthe receiver, the byte count
should be set to some number larger than any packet
that will be receivq up to 64K. If not usingthe Done
flag, then GSCservicingwouldbe drivenby the receive
Done (RDN) flag and/or interrupt. RDN is set when
the EOF is detected.Whenusingthe RDN tlag, RFNE
ahould also be checkedto insure that all the data has
been emptiedout of the receive FIFO.
The byte count registeris used for all transmissionsand
this means that all packetsgoingout will have to be of
the same length or the length of the packet to be sent
willhave to be knownprior to the start of transmission.
When using the DMA channels to seMce the GSC
transmitter, there is no practical way to disable the
Done flag. This is because the transmit done fig
(TDN) is set whenthe transmit FIFO is emptyand the
last messagebit has been transmitted. But, when using
the DMA channel to service the tranann 'tier, loads to
the TFIFO continue to occur until the byte count
reaches O.This makes it impossibleto use TDN as a
flag to stop the DMA transfers to TFIFO. It is possible
to examin e some other registers or conditions,such as
the current byte count, to deterrmn " e when to stop the
DMA transfersto TFIFO, but this is not recommended
as a way to seMce the DMA and GSC whentransmit-
ting becausefrequentreadingof the DMA registerswill
cause the effectiveDMA transfer rate to slow down.
When using the DMA chann~ ini-tion of the
GSC wouldbe exactfythe same as normal exceptthat
TSTAT.O= 1 (DMA), this informs the GSC that the
DMA channelsare goingto be used to servicethe GSC.
Although only TSTATis written to, betb the receiver
and transmitter use this same DMA bit.
The interrupts EGSTE (IEN1.5), GSC transmit error;
EGSTV (IEN1.3), GSC transmit valid; EGSRE
(IENI.1), GSC receive erro~ and EGSRV (IEN1.0),
GSC receivevalid;needto be enabled.The DMA inter-
rupts are normally not used when servicingthe GSC
with the DMA channels.To ensure that the DMA in-
terrupts are not reapondedto is a function of the user
sotlware and shoufd be checked by the software to
make sure they are not enabled.Priority for these inter-
rupts can also be set at this time. Whether to w high
or low priority needs to be decidedby the user. When
respondingto the GSC interrupts, if a buffer is being
used to store the GSCinformation,then the DMA reg-
isters used for the bufferwill probablyneed updating.
After this initialization,all that needs to be done when
the GSC is actuaffygoingto be used is: load the byte
count, set-up the source addreasesfor the DMA chan-
nel servicingthe transmitter, set-up the destinationad-
dresses for the DMA channel servicing the receiver,
and start the DMA transfer. The GSC enable bits
should be set iirst and then the GO bits for the DMA.
This initiates the data transfem.
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