Intel MCS 51 User Manual page 320

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83C152 HARDWARE DESCRIPTION
Figure 4.11showsthe three tasks to which the internal
bus of the 8XC152can be dedicated. In this tigurq
Instruction Cycle means the complete execution of a
single instruction, whether it takes 1, 2 or 4 machine
cycles.DMA Cyclemeans the transfer of a singledata
byte from sourceto destination,whetherit takes 1 or 2
machinecycles.Each time a DMA Cycleor an Instruc-
tion Cycleis executed,on-chiparbitration logic deter-
mines which type of cycle is to be executednext.
Note that when an instruction is executed, if the in-
struction wrote to a DMA register (definedin Figure
4.1 but excludingPCON), tien snother instruction is
executedwithout further arbitration.Therefore, a sin-
gle write or a series of writes to DMA registers will
preventa DMA from takingpla% and will continueto
prevent a DMA from taking place until at least one
instruction is executed which does not write to any
DMA register.
The logicthat determineswhetherthe next cyclewillbe
a DMAOcycle,a DMAI cycle,or an Instruction Cycle
is shownin Figure 4,12as a pseudo-HLLfunction.The
statementsin Figure 4.12 are executedsequentiallyun-
lessan "it" conditionis sstisfi~ in whichcase the cor-
responding"return" is executedand the remainder of
the function is not. The return value of O, 1, or 2 is
passed to the arbitration logicblockin Figure 4.11 to
detemninewhich exit path from the block is used.
The return value is based on the conditionof the 00
bit for each channel, and on the value returned by an-
other functio~ named modedogic (). The algorithm
for mode-logic () is the samefor both channels.The
function is shown in Figure 4.13 as a pseudo-HLL
functionjmode-logic (n), wheren = Owhenthe func-
tion is invokedfor DMA cbannelO,and n = 1 when
it'sinvokedfor DMA channel 1.The valuereturned by
this t%nctionis either Oor 1, and will be passed on to
the DMA arbitration logicin Figure4.12.
Note that the arbitration logicas shownin Figure 4.12
alwaysgivesprecedenceto channelOover channel 1. If
000 is set and mode-logic (0) returns a 1, then a
DMAOcycle is called withouttiwther referenm to the
situation in channel 1. That is not to say a DMAI Cy-
cle will be interrupted once it has begun.Once a cycle
has begun,be it an InstructionCycleor a DMA Cycle,
it will be completedwithoutinterruption.
The statements in modedogic (n), Figure4.13,are ex-
ecutedsequentiallyuntil an "if' condition,basedon the
DMA mode pro grsmmed into DCONn, is sstistied.
For example, if the channel is configured to Burst
mode,then the first if-conditionis satisfied,so the "re-
turn 1" exrmssion is executedand the remainderof
the
fimctioni; not.
arbitration-logic:
if (GOO = 1 .AND. mode-logic (0) = 1) return O;
if (GO1 = 1 .AND. modeJogic (1) = 1) return 1 ;
else return 2;
end arbitration-logic;
Figure 4.12. DMA Arbitration Logic
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