Cmod - Intel MCS 51 User Manual

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8XC51FXHARDWARE DESCRIPTION
CH is incremented after two oscillator periods when The CCON register, shown in Table 11, contains two
CL OVdOWS.
more bits which are associated with the PCA timer/
counter. The CF bit gets set by hardwme when the
The mode register CMOD contains the Count Puke counter overtlows, and the CR bit is set or cleared to
8elect bits (C%l and CPSO)to specify the clock input. turn the counter on or off. The other five bits in this
CMOD is shown in Table 10. This register also eon-
register are the event figs for the compare/capture
tains the ECF bit which enables the PCA counter over- moduks and will be diseuaaedin the next section.
flow to generate the PCA
interrupt. In addition, the
user
has the option of turning off the PCA timer during
Idle Mode by setting the Counter Idle bit (CIDL). The
Watchdog Timer Enable bit (WDTE) will be diaoussed
in a later section.
Table 10. CMOD: PCA Counter Mode Register
CMOD
Address= OD9H
ResetValue= OOXX XOOOB
Not Bit Addressable
CIDL WDTE — — —
CPS1 CPSO
ECF
Bit
7 6 5 4 3 2
1 0
SYmbol Function
CIDL CounterIdlecontrol:CIDL= Oprograms the PCACountertocontinue functioning during
idleMode.CIDL= 1programs it to begatedoff duringidle.
WDTE WatchdogTimerEnable: W DTE= Odiaebles Watchdog Timerfunctionon PCAModule4.
WDTE= 1 enablesit.
—
Notimplemented, r esewed for futureuse.*
CPS1 PCACountPuleeSelectbit 1.
CPSO
PCACountPulseSelectbitO.
CPS1 CPSO Selected PCA Input**
o
0 Internalclock,Fosc+ 12
0 1 Internalclock,FOSC+4
1
0
Timer Ooverflow
1 1 External
clockat ECVP1.2 pin(max.rate = Fosc+8)
ECF
PCAEnableCounter Overflow interrupt ECF= 1 enables CFbit in CCONto generatean
interrupt.ECF= Odisables thatfunctionof CF.
NOTE
*Uaer s oftware s hould notwritsIs to raaerved bik. ThSSS b itsmaybe used
in futureS051 familyproduetato invoke
new featurea.
In that ease, the reset or inaetkfe value of the new bit will be O, and ifs active value will be 1. The value
read from a reaerved bit is indeterminate.
*FOSC = oscillator frequeney
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